A comparison between Lattice, Cascade and Direct-form FIR filter structures by using a FPGA bit-serial Distributed Arithmetic implementation

In this paper, several bit-serial, high-order implementations of cascade, lattice and direct- form FIR filters using Distributed Arithmetic (DA) are studied. Although lattice and cascade structures present many interesting properties related to quantification error and stability, they DA versions has not been thoroughly compared. Three types of filters with their particular bit- serial DA model error have been constructed using an ALTERA 10K50 FPGA and they area- time figure is analysed. Mains results show that a 60th order bit-serial cascade and direct-form implementation with nearly 4MHz and a 40th order lattice structure with 7.5MHz can be implemented. Moreover, in contrast to the first structures, the lattice filter presents the lower quantification error.