A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Koo Il Seo,Balasubramanian S Haran, Deepika Gupta,Di Guo,T Standaert,R Xie,Huiling Shang,Emre Alptekin, D I Bae, Gihyun Bae, Carol A Boye,Hong Cai, D Chanemougame, Roger Chao,Kwangting Cheng,Jeonwook Cho,Kwonhue Choi,Bassem Hamieh, J G Hong,Terence B Hook, L Jang, Jinyong Jung, R Jung, Daewoo Lee, B Lherron,R Kambhampati,Bumki Kim,Heonhwan Kim, Kunsu Kim,Tae Seon Kim,Seokbum Ko,Fee Li Lie, Deming Liu, H Mallela,Edward J Mclellan, Sharad Mehta,Pietro Montanini, Marta Mottura, J Nam, Seokho Nam, Frederick Nelson,Injo Ok, Changjoon Park, Yuseop Park,A Paul,C Prindle,Ravi P Ramachandran,Muthumanickam Sankarapandian, Viraj Y Sardesai,Andreas Scholze,S C Seo, J K Shearer,R G Southwick,Raghavasimhan Sreenivasan, S Stieg,Jay W Strane,Xinghua Sun,Moon Gyu Sung,Charan Veera Venkata Satya Surisetty,Gen Tsutsui,Nagesh K Tripathi,Reinaldo A Vega,Christopher Waskiewicz, M Weybright,C C Yeh,H Bu, Steven M Burns,D Canaperi,Mehmet Ali Celik,Matthew E Colburn,Hemanth Jagannathan, S Kanakasabaphthy, W Kleemeier,Lars W Liebmann, D Mcherron, P Oldiges,Vamsi Paruchuri,T Spooner,J H Stathis, R Divakaruni, T R Gow,John Iacoponi, J S Jenq, R Sampson,Manish Khare

VLSI Technology（2014）

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摘要

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

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关键词

mosfet,sram chips,lithography,low-power electronics,metallisation,silicon-on-insulator,finfet devices,sram bit cell,contacted poly pitch,metallization pitch,multi workfunction gate stack,optical patterning limit,size 10 nm,size 48 nm,size 64 nm,static noise margin,voltage 0.75 v,voltage 140 mv,low power electronics,very large scale integration,silicon on insulator,logic gates,metals,cmos integrated circuits

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