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Terence B. Hook

IBM General Technology Division, Department G39, Bldg 972-2, Essex Junction, VT 05452, U.S.A.

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Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating

Charu Gupta, Anshul Gupta,Reinaldo A. Vega,Terence B. Hook,Abhisek Dixit

IEEE Transactions on Electron Devices, no. 5 (2020): 2208-2212

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Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating

Charu Gupta, Anshul Gupta, Reinaldo A. Vega,Terence B. Hook,Abhisek Dixit

IEEE Transactions on Electron Devices, pp.1-5, (2020)

Bibtex

Toward Microwave S- and X-Parameter Approaches for the Characterization of Ferroelectrics for Applications in FeFETs and NCFETs

Zhi Cheng Yuan,Prasad S. Gudem, Michael Wong, Ji Kai Wang,Terence B. Hook,Paul Solomon,Diego Kienle,Mani Vaidyanathan

IEEE Transactions on Electron Devices, no. 4 (2019): 2028-2035

EIWOSBibtex

Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating

Anshul Gupta, Charu Gupta,Reinaldo A. Vega,Terence B. Hook,Abhisek Dixit

IEEE Transactions on Electron Devices, no. 5 (2019): 2075-2080

EIWOSBibtex

Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and Beyond

Robert H. Dennard,Takashi Ando,Isaac Lauer,Terence B. Hook

IEEE Journal of the Electron Devices Society, (2018): 551-556

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Impact of Line and Via Resistance on Device Performance at the 5nm Gate All Around Node and Beyond

Nicholas A. Lanzillo, Koichi Motoyama,Terence B. Hook,Larry Clevenger

international interconnect technology conference, (2018)

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Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

Ishita Jain, Anshul Gupta,Terence B. Hook,Abhisek Dixit

IEEE Transactions on Electron Devices, no. 10 (2018): 4238-4244

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OFF-State Leakage and Performance Variations Associated With Germanium Preamorphization Implant in Silicon–Germanium Channel pFET

Vishal A. Tiwari,Rama Divakaruni,Terence B. Hook,Deleep R. Nair

IEEE Transactions on Electron Devices, no. 9 (2018): 3654-3661

EIWOSBibtex

3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes

Anil K. Bansal, Charu Gupta,Anshul Gupta, Ramendra Singh,Terence B. Hook,Abhisek Dixit

IEEE Transactions on Electron Devices, no. 3 (2018): 1246-1252

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Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET

R. Singh, K. Aditya, S. S. Parihar,Y. S. Chauhan,R. Vega,T. B. Hook,A. Dixit

IEEE Electron Device Letters, no. 8 (2018): 1246-1249

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Series Resistance Reduction With Linearity Assessment for Vertically Stacked Junctionless Accumulation Mode Nanowire FET

Anil K. Bansal,Manoj Kumar, Charu Gupta,Terence B. Hook,Abhisek Dixit

IEEE Transactions on Electron Devices, no. 8 (2018): 3548-3554

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Impact of Short-Wavelength and Long-Wavelength Line-Edge Roughness on the Variability of Ultrascaled FinFETs

Michael Wong,Kyle David Holland, Sam Anderson, Shahriar Rizwan, Zhi Cheng Jason Yuan,Terence B. Hook,Diego Kienle,Prasad S. Gudem,Mani Vaidyanathan

IEEE Transactions on Electron Devices, no. 3 (2017): 1231-1238

Cited by2EIWOSBibtex

Channel Material Dependence of Wave Function Deformation Scattering in Ultrascaled FinFETs

Michael Wong,Kyle David Holland, Ji Kai Wang, Thomas Cam,Terence B. Hook,Diego Kienle,Prasad S. Gudem,Mani Vaidyanathan

IEEE Transactions on Electron Devices, no. 12 (2017): 5107-5113

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Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

Nicolas Loubet,Terence B. Hook, Pietro Montanini, C.-W. Yeung,Sivananda K. Kanakasabapathy, M. Guillom, Tenko Yamashita, J. Zhang, X. Miao, Junli Wang, A. Young, Robin Chao

symposium on vlsi technology, (2017)

Cited by5Bibtex

Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets

Terence B. Hook

Joule, no. 1 (2017): 1-4

Cited by73Bibtex

Reliable airgap BEOL technology in advanced 48 nm pitch copper/ULK interconnects for substantial power and performance benefits

Christopher J. Penny,Stephen M. Gates,Brown Peethala, Joe Lee,Deepika Priyadarshini,Son Van Nguyen,Paul S. McLaughlin,E. Liniger,C.-K. Hu, Lawrence A. Clevenger,Terence B. Hook,Hosadurga Shobha

international interconnect technology conference, pp.1-4, (2017)

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Analytical Modeling of Parasitic Capacitance in Inserted-Oxide FinFETs

Ramendra Singh,Anshul Gupta, Charu Gupta, Anil K. Bansal,Terence B. Hook,Abhisek Dixit

IEEE Transactions on Electron Devices, no. 12 (2017): 5274-5278

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Advanced FDSOI design: The U-channel device for 7nm node and beyond

Robert H. Dennard, Takashi Ando,Isaac Lauer,Terence B. Hook

ieee soi 3d subthreshold microelectronics technology unified conference, (2017)

Bibtex

Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs

Zhi Cheng Yuan, Shahriar Rizwan, Michael Wong,Kyle David Holland, Sam Anderson,Terence B. Hook,Diego Kienle, Serag Gadelrab,Prasad S. Gudem,Mani Vaidyanathan

IEEE Transactions on Electron Devices, no. 10 (2016): 4046-4052

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Vertical Slit FET at 7-nm Node and Beyond

Ping-Lin Yang,Terence B. Hook,Philip J. Oldiges,Bruce B. Doris

IEEE Transactions on Electron Devices, no. 8 (2016): 3327-3334

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