Low cost 65nm CMOS platform for Low Power & General Purpose applications

F Arnaud,B Duriez,B Tavel,L Pain, J Todeschini, M Jurdit,Yves Laplanche,F Boeuf,F Salvetti, D Lenoble, J P Reynard, F Wacquant,P Morin,N Emonet, D Barge,M Bidaud, D Ceccarelli, P Vannier,Yannick Loquet, H Leninger, F Judong,C Perrot, Isabelle Guilmeau, R Palla, A Beverina, V Dejonghe, M Broekaart, V Vachellerie,R A Bianchi,B Borot,T Devoivre, N Bicais,D Roy, M Denais, K Rochereau,R Difrenza,N Planes,Hugues Brut, L Vishnobulta, D Reber,P A Stolk,M Woo

ieee（2004）

引用 41|浏览19

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摘要

A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 μm2 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 μm2 bit-cells with 240mV of SNM and 35 μA of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 μA/ μm and 400 μA/ μm for NMOS and PMOS respectively are obtained at Vdd = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. μm) and analog voltage gain factor (Gm/Gd>2000 for L = 10 μm) at the leading edge for this process technology. NBTI criteria at 125°C for both LP and GP transistors are presented and characterized at overdrive conditions.

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关键词

cmos integrated circuits,sram chips,1.2 v,240 mv,65 nm,sram bit-cells,analog transistor parameters,low cost 65nm cmos platform,transistor drive currents,etching,voltage,cmos technology,silicon

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