A conventional 45nm CMOS node low-cost platform for general purpose and low power applications

F Boeuf,F Arnaud,M T Basso,D Sotta,F Wacquant, Jose M De La Rosa, N Bicaislepinay,H Bernard, J J Bustos,Serdar Manakli, M Gaillardin, John M Grant,Thomas Skotnicki,B Tavel,Bart Duriez,M Bidaud,P Gouraud,C Chaton,P Morin,J Todeschini,M Jurdit,L Pain, V Dejonghe,R Elfarhane, S Jullian

international electron devices meeting（2004）

引用 58|浏览46

暂无评分

摘要

In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demonstrated. GP nFET/pFET devices feature Ion= 820μA/μm/340 μA/μm at Ioff = 20nA/μm at Vdd=1.0V. RO features Tp < 10ps. LP devices feature Ion= 505 μA/μm 1240 μA/μm at Ioff = 0.1 nA/μm at Vdd= 1.2V. In addition, high-voltage 50A/2.5V devices are made to complete the CMOS platform.

查看译文

关键词

cmos integrated circuits,low-power electronics,nanotechnology,2.5 v,45 nm,50 a,cmos,lp devices,sion gate oxide,conventional bulk approach,general purpose application,low power applications,low-cost platform,nfet/pfet devices,process induced strain,shallow junctions,high voltage,low power electronics

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要