Efficient modeling methodology and hardware validation of glass-ceramic based wiring for high-performance single- and multi-chip modules

Ceramic-based wiring has been used in IBM in high-performance multi-chip module (MCM) carriers since the early 1980s. These types of carriers can provide very high wiring and power densities. Conductors are generally screened on individual ceramic sheets that are laminated and sintered at greater than 900° C. The high temperature process requires the use of copper paste metallization with higher resistivity than bulk copper and the punched-via fabrication imposes the use of meshed ground planes. Typical MCMs can have close to 100 layers [George Katopis (1998)] with 200-400 μm via pitch. In the case of single-chip modules (SCM), hundreds of signal I/O's on 100-200 μrn pitch redistribute to the coarser module wiring. The fan-out, the hollow shielding, and the sparse and long vias generate large signal distortion and crosstalk between signal layers and via columns. This paper describes the modeling and measurement of representative glass-ceramic based wiring for both SCM and MCM applications.