Stress Analysis of Embedded Active Devices in Substrate Cavity for System-On-Package (SOP)

The effect of thinning down the chip thickness, will affect the stress pattern in the chip and causes the chip to deform locally when the thickness of the chip is thinner than a certain critical value. Such a local deformation may cause sharp gradient of residual stress around the solder bumps and thus, various failures. This paper shows that by considering the effect of solder bumps on a 50 mum chip, the stress magnitude increases by almost double. In addition, the normal stress (sigmax) in the 50 mum chip is increased by 94% with increasing coefficient of thermal expansion of the embedded material properties. By moving the same 50 mum chip on top surface along the diagonal and side of the BT substrate, it is observed that the stress in the chip remains unchanged. Finally both the shape of parallelogram and square 50 mum chip have a lower stress magnitude as compared to other shapes.