Engineering Substrates for 3D Integration of III-V and CMOS

Our direct growth approach of integrating compound semiconductors (CS) and silicon CMOS is based on a unique silicon template wafer with an embedded CS template layer of Germanium (Ge). It enables selective placement of CS devices in arbitrary locations on a Silicon CMOS wafer for simple, high yield, monolithic integration and optimal circuit performance. HBTs demonstrate a peak current gain cutoff frequency ft over 200 GHz. To the best of our knowledge this represents the first demonstration of an InP-based HBT fabricated on a silicon wafer.