Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning
Proceedings of SPIE(2009)
摘要
Self-Aligned Double patterning (SADP) technology has been identified as the main stream patterning technique for
NAND FLASH manufacturers for 3xnm and beyond. This paper demonstrates the successful fabrication of 32nm halfpitch
electrical testable NAND FLASH wordline structures using a 3-mask flow. This 3-mask flow includes one critical
lithography step and two non-critical lithography steps. It uses a positive tone (spacer as mask) approach to create 32nm
doped poly wordlines. Electrical measurements of line resistance are performed on these doped poly wordlines to
demonstrate the capability of this patterning technique. Detailed results and critical process considerations, including
lithography, deposition and etch, will be discussed in this paper.
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关键词
resistance,lithography,fabrication
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