First Experimental Demonstration of Ge 3D FinFET CMOS Circuits
2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY)(2015)
摘要
We report the first experimental demonstration of Ge 3D CMOS circuits, based on the recessed fin structure. Both n-FinFETs and p-FinFETs with channel length (L ch ) from 200 to 20 nm and fin width (W Fin ) from 60 to 10 nm are realized on a Ge-on-insulator (GeOI) substrate. The Ge FinFETs show superior gate electrostatic control over planar devices and sub-threshold slope (SS) as low as 93 and 73 mV/dec are obtained on n- and p-FETs, respectively. Combining the n- and p- type 3D devices together, the FinFET CMOS inverters have high voltage gain up to 34 V/V at V DD of 1.4 V, delivering more than 200% improvement over the planar ones at the same L ch of 200 nm. Scalability studies are also carried out for both types of FinFETs in terms of L ch and W Fin .
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关键词
3D FinFET CMOS circuits,gate electrostatic control,planar devices,sub-threshold slope,FinFET CMOS inverters,voltage 1.4 V,Ge
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