Wafer-Level Heterogeneous Integration of GaN HEMTs and Si (100) MOSFETs

This letter demonstrates a new technology for the heterogeneous integration of GaN and Si devices, which is scalable at least up to 4-in wafers and compatible with conventional Si fabrication. The key step in the proposed technology is the fabrication of a Si (100)-GaN-Si hybrid wafer by bonding a silicon (100) on insulator (SOI) wafer to the nitride surface of an AlGaN/GaN on Si (111) wafer. A th...