Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models.

Real number modeling of analog circuits in hardware description languages (HDLs) has become more common as a part of mixed-signal SoC validation. We propose two methods that both improve the fidelity and simulation speed, and make the event-driven, piecewise linear (PWL) analog functional models easier to write. First we use the accuracy set by users to dynamically determine when a new output segm...