An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS

Mark A. Ferriss,Jean-Olivier Plouchart,Arun Natarajan,Alexander Rylyakov,Benjamin D. Parker,Aydin Babakhani,Soner Yaldiz,Bodhisatwa Sadhu,Alberto Valdes-Garcia,José A. Tierno,Daniel J. Friedman

VLSIC（2012）

引用 5|浏览49

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关键词

CMOS integrated circuits,calibration,nanoelectronics,phase locked loops,phase noise,silicon-on-insulator,voltage-controlled oscillators,SOI CMOS,VCO small signal gain variation,bandwidth self-calibration scheme,dual-loop PLL,dual-loop architecture,frequency 10 MHz,frequency 20.1 GHz to 26.7 GHz,integral path measurement,integral path self-calibration scheme,loop transfer function,low noise PLL,noise figure 2.4 dB to 1 dB,phase noise,size 300 mm,size 32 nm,

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