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Detection of IJTAG Attacks Using LDPC-based Feature Reduction and Machine Learning

2018 IEEE 23rd European Test Symposium (ETS)(2018)

Cited 7|Views17
Key words
machine learning,high-dimensional data,on-chip detection,high-dimensional but sparse data,low-density parity-check matrix,IJTAG functionality,detection accuracy,IJTAG attacks,LDPC-based feature reduction,IEEE 1687 standard,IEEE 1149,embedded instruments,reconfigurable scan networks,segment insertion bit,scan-mux control bit,SIB/SCB network,credential data,test data register,reverse engineering IP design
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