Characteristics of Tunnel Field-effect Transistors under Power-on Electrostatic Discharge and Electrical Overstress Conditions

The power-on electrostatic discharge (ESD) and electrical overstress (EOS) events are causing an increasing number of failures in modem integrated circuits (ICs). Tunnel field-effect transistors (TFETs) are considered as a better choice than shallow trench isolation diodes in whole-chip ESD protection networks. We have investigated the characteristics of TFETs under power-on ESD and EOS conditions by numerical simulation. The impact of an elevated ambient temperature, variations in current rise time and discharge duration, and the device structure on the triggering voltage and failure current are evaluated. The obtained results are discussed with detailed physical insights.