Recovery-Aware DRM for Near-Threshold Dark Silicon Processors

To further reduce powers for many applications, ultra-low power designs become necessary. Recent research has led to sub-threshold region where CMOS circuits are found to be capable of operating with a supply voltage of less than 200 mV. The theoretical lower limit of V dd has been determined to be 36 mV (Swanson and Meindl, IEEE J Solid-State Circuits 7:146–153, 1972). But at such low voltages, a leakage power dissipation increases drastically making the reduction in dynamic power insignificant. Also the circuit delay increases rapidly as the supply voltage is scaled down, resulting in decreased operation frequency or performance of the circuits.