One-step TSV process development for 4-layer wafer stacked DRAM

The 3D stacked DRAM is an essential key module for high-performance computing systems. However, the cost increase due to 3D slacking limits its applications. The current 3D stacking technology requires front-side and backside microbumps, temporary bonding and debonding, time-consuming chip stacking etc., as additional process steps. In this paper, a 4-layer one-step TSV fabrication process is studied, enabling only one-time TSV fabrication combined with bumpless wafer-to-wafer stacking. Multi-stack layer dry etching is successfully demonstrated with photoresist masks by optimizing Si, oxide, and Al etching. Sidewall angles were controlled in the order of Si>SiO2>Al to balance aspect ratio and TSV/Al-pad connection. Cu filling is done by electroplating, and right filling property and good contact between Al sidewall and TSV are confirmed by cross-sectional analysis.