Dummy Gate Amorphous Silicon CMP Using In-situ Profile CLC Endpoint System for Advanced FinFET

The Fin Field Effect Transistor (FinFET) has been introduced at 22 nm node of logic devices. Its three dimensional geometry provides many advantages for the device performance. The FinFET remains the main stream down to 7 nm node. New chemical mechanical planarization (CMP) steps have been implemented to enable the FinFET fabrication. One of them is the amorphous silicon (a-Si) CMP process. It aims to planarize the a-Si layer stopping on a target thickness before dummy gate patterning. The challenges in this CMP step are planarization efficiency, process control and defectivity. The specifications for the post CMP non-uniformity are very tight, such as +/- 5 nm within die (WID), within wafer (WIW) and wafer to wafer (WTW) a-Si thickness variation. In this study, we have evaluated one step a-Si CMP process using an optical endpoint system with in-situ profile closed loop control (CLC) on EBARA Model F-REX300X CMP tool for 7 nm and 14 nm node FinFET devices. Our results indicate that this advanced system can significantly improve the WIW and WTW a-Si thickness control and meet the strict specifications for the current and future technology node FinFET devices. Keywords: a-Si CMP, SOPM CLC, FinFET