Ferroelectric FET Threshold Voltage Optimization for Reliable In-Memory Computing.

Ferroelectric FET (FeFET) emerges as a highly promising candidate for in-memory computing due to its outstanding performance, superior energy efficiency and great scalability. For FeFET, generally the memory window, i.e., the separation between the two threshold voltage (V-TH) states, is of interest. The absolute value of the low-V-TH and high-V-TH states are generally not scrutinized. However, in this work, we demonstrate that a proper engineering of V-TH is necessary to ensure correct array operation for in-memory computing applications. We highlight that for all the current-based operations, it is necessary to keep both the V-TH states positive to cut off the leakage for grounded unselected cells. To reach that design target, we systematically evaluate various design options for V-TH engineering, including the gate metal work function, the body bias, and the buried oxide thickness, in a fully-depleted silicon-on-insulator (FDSOI) FeFET using calibrated TCAD simulations. We establish the design guidelines for V-TH engineering to ensure successful operation of in-memory computing applications.