Memory Array Demonstration of Fully Integrated 1T-1C FeFET Concept with Separated Ferroelectric MFM Device in Interconnect Layer.
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)(2022)
摘要
In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.
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关键词
FeFET,ferroelectric memory,hafnium oxide
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