Crosstalk Mitigation for High Speed SerDes Applications on FCBGA Package

Flip-chip ball grid array (FCBGA) is a good and popular package solution for high speed serializer/ deserializer (SerDes) applications. However, the crosstalk performance gets worse at higher frequency, especially a 64 GHz peak is usually observed. Many substrate design components will affect electrical performance, such as package thickness, material, ball size, void size, and routing topology. This paper investigates several design schemes to mitigate the peak of crosstalk issue. The simulation results show that both far-end crosstalk (FEXT) and near-end crosstalk (NEXT) can be significantly improved by 10.9 dB and 4.0 dB, respectively. Signal integrity of high data rate signals can be optimized consequently by applying those design factors.