Demonstration of Ferroelectric-Gate Field-Effect Transistors With Recessed Channels

This letter describes a novel ferroelectric-gate field-effect transistor (R-FeFET) with a recessed circular channel aiming to improve memory window (MW), program/erase speed, long-time retention, and endurance simultaneously. Through the pulsed program/erase operations, we confirmed that the R-FeFET exhibited enhanced MW and faster operation compared with conventional planar FeFET (P-FeFET) because the electric field (e-field) is more concentrated at the ferroelectric (FE) region with the smaller radius closer to the gate metal. Furthermore, we proved that the R-FeFET can maintain the MW more endurance cycling (over similar to 10(7) cycling) than P-FeFET with the same MW, which results from the mitigated trapping of holes, which are generated at the substrate by injected hot electrons from gate metal, to interlayer (IL) and FE owing to the reduced e-field at channel-side FE layer and IL.