CMOS-Fabricated Ring Surface Ion Trap with TSV Integration

Peng Zhao,Yu Dian Lim,Hongyu Li,Jean-Pierre Likforman,Luca Guidoni, Lilay Gros Desormeaux,Chuan Seng Tan

2023 International Electron Devices Meeting (IEDM)（2023）

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摘要

We present the design, fabrication, and test of ring surface trap on 12-inch wafers with a CMOS process. The design is based on Through Silicon Vias (TSV) interconnects. Up to 200 ions were loaded and cooled; preliminary compensations of electrostatic potential imperfections show that rotational symmetry can be partially restored.

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关键词

Ion Trap,Through Silicon Via,Rotational Symmetry,Fabrication Process,Waveguide,Finite Element Model,Focal Length,Quantum Information,Part Of Ring,Ring Electrode,Trapping Potential,Polyimide Layer,Flip-chip,Photonic Integration

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