Signal Integrity Design and Analysis of Universal Chiplet Interconnect Express (UCIe) Channel in Silicon Interposer for Advanced Package

2023 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)(2023)

引用 0|浏览0
暂无评分
摘要
In this paper, we design and analyze the Universal Chiplet Interconnect Express (UCIe) channel considering signal integrity (SI) in silicon interposer for advanced package. In a chiplet system, various chips from other vendors are integrated into one package using common UCIe channels. Silicon interposer is a promising advanced package that can achieve high bandwidth with high channel density. First of all, we investigate the possible interconnect dimensions considering a rout-ability in UCIe specification. Then, we propose transmission line-based interconnect structures with different signal/ground patterns for 2- and 3-layer routing in 32 Gbps operation. Since the advanced package has an unterminated system, the voltage transfer function is used as the SI specification of interconnect in a frequency domain. Also, bump arrays are included at Tx and Rx side in a full channel eye-diagram simulation. We verified the crosstalk in an interconnect is the main bottleneck for channel design, and the bump causes loss by adding a capacitance than the crosstalk effect. The grounded coplanar waveguide (GCPW) based interconnect can be the promising solution with a minimum 2 metal layers for signals in a silicon interposer.
更多
查看译文
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要