K. L. N. College of Engineering

The various industrial sectors stand to gain significant advantages from the implementation of the Industrial Internet of Things (IIoT). Furthermore, given restricted channel materials, it is challenging to make the globe’s most effective choice in distributed wireless sensor networks (DWSN). Industrial sensor networks are susceptible to complicated industrial circumstances which are susceptible to an integration of various signal patterns. The complex interference from multiple signals can significantly lower the effectiveness of the classification of signals on industrial equipment, requiring a significant process of training that characteristics can be obtained. Furthermore, generalized envelope squared spectrum (GESS) is supplied for increased reconstruction of transmission signals. In this study, we propose a machine learning-based model an adaptive modulation-based simplified deep convolutional neural network (AM-SDCNN) for classifying signal nodes DWSN. Frequency reduction and sampling conditioning are implemented to receive signals from nodes, enabling the generation of intelligent signal representations. The aggregation center gets the output of the signal categorization process carried out by every single sensor node over a network. The simulation demonstrates that the suggested AM-SDCNN technique has beneficial performance in signal classification. Particularly, the suggested technique does not need transmitting signals from nodes to the aggregation center, which can preserve the privacy of industrial information.

Scaling CMOS technology is being more threatening and therefore limited due to power dissipation, leakages and physical consideration at the nano-scale. A promising post-CMOS computing model that can be used to achieve ultra-low-power computation through encoding binary information using electron polarization, and not current flow, is Quantum-Dot Cellular Automata (QDCA). In this paper, the QDCA circuit design algorithm discussed is an energy-efficient algorithm that targets optimization of the majority logic designs and reduction of the unwanted interactions of cells. The suggested method reinvents Boolean logic based on majority algebra and utilizes layout-level optimization to minimize the number of cells, circuit area, latency and energy dissipation. It has been shown through simulation that the proposed designs can provide scalings in cell count (about 27-30 percent), layout area (more than 30 percent) reduction, latency (approximately 32) reduction, and energy dissipation (nearly 35 percent) reduction over conventional QDCA implementations. These advances underscore the usefulness of the suggested methodology towards creating scalable, low-power nano-scale digital circuits that can be used in the next-generation computing systems.

Electric Vehicles (EVs) require stable auxiliary power supplies to operate electronic subsystems such as controllers, sensors, communication modules, and display units. However, fluctuations in the EV battery voltage due to load variations may affect the reliable operation of these sensitive electronic components. To overcome this issue, a digitally controlled DC–DC voltage regulation system is proposed. In this project, a PWM-based closed-loop buck converter is implemented using an Arduino UNO. The system is designed to operate with an EV battery as the primary DC input source. A discrete buck converter consisting of a MOSFET, inductor, diode, and capacitor is used as the power stage to step down and regulate the voltage. The output voltage is sensed through a voltage divider circuit and fed to the Arduino ADC for feedback control. The system can generate selectable output voltages such as 3.3V, 5V, and 12V, which are commonly used in EV electronic subsystems. For demonstration, components such as LED indicators and a buzzer are connected as loads representing devices operating at these voltage levels. The output voltage can also be modified through software programming, making the system flexible and user configurable for different voltage requirements. Based on the selected reference voltage, the Arduino adjusts the PWM duty cycle to maintain the required output. The regulated voltage is displayed on an LCD for real-time monitoring. The proposed system demonstrates a flexible, user-efficient, and digitally controlled auxiliary voltage regulation system for EV applications.

The paper proposes a hybrid AI framework that combines temporal and graph measures to measure financial risk in dynamic nonstationary markets. The structure has a temporal transformer encoder, a relation graph neural network (GNN) and multi-task probabilistic prediction heads to jointly score the probability of default (PD), value at risk (VaR), conditional value at risk (CVaR), and expected losses. The system uses many kinds of information. This involves market signals, economic information, firm information, randomly generated news-based features, and specific exposure networks. Our preprocessing pipeline aligns different time series at various resolutions. We use four concept-drift handling mechanisms namely online adaptation, divergence detection, ensembles and stress simulation for augmenting. This bolsters strength as market circumstances shift. The proposed model surpasses statistical baselines including CR, deep-learning baselines such as LSTM and GNN baselines like PGNN on three datasets (1,500 global firms over crisis regimes). The architecture improves the performance of traditional models by enhancing the PD AUC by 12.6 % as well as reducing the forecast errors of VaR and CVaR by 28-50 % and generating large expected-loss improvements at the portfolio level. There are various methods for explaining GNN outputs including SHAP feature attributions, GNN edge-level interpretability, and rule-based surrogate governance models that satisfy auditability requirements. According to the results, the novel temporalgraph multi-tasking system for systematic financial risk assessment is more flexible, interpretable and accurate approaches real-world volatility and systemic interdependence in comparison to existing methods.

As the scaling limitations of conventional CMOS technology increasingly affect power efficiency and performance, alternative nano-scale computing paradigms have emerged as promising solutions. Quantum-dot Cellular Automata (QCA) is a post-CMOS technology that represents binary information through electron polarization rather than current flow, enabling ultra-low power dissipation and high-speed operation. In parallel, Vedic multiplication based on the Urdhva Tiryagbhyam sutra offers an efficient arithmetic technique by enabling parallel generation of partial products. The Vedic multiplication algorithm is systematically translated into logical expressions and implemented using QCA majority gates and inverters with appropriate clocking schemes. The proposed architecture exploits the inherent parallelism of the Vedic sutra to reduce computational delay and circuit complexity. The design is modeled and simulated using QCA Designer to verify functional correctness. Simulation results demonstrate that the proposed QCA-based Vedic multiplier achieves improved speed and reduced structural complexity compared to conventional CMOS-based multiplier architectures. Due to its low-power operation and parallel processing capability, the proposed design is well suited for high-speed arithmetic units in future nano-scale and energy-efficient computing systems.