三安光电股份有限公司

This brief presents an 8-bit column pitch-matched charge injection (CI) SAR ADC specifically designed for computing-in-memory (CIM) macros. We propose an area-efficient built-in calibration loop that reuses the DAC array to mitigate offset effects and enhance inference accuracy, significantly reducing the digital logic and trimming circuit area overhead compared to conventional background/foreground calibration methods. To preserve offset and quantization results, we implement dedicated digital logic featuring an optimized data buffer chain with local positive feedback for node voltage stabilization. Fabricated in 65nm CMOS technology, the ADC occupies 0.0013mm2 while demonstrating significant performance improvements: offset reduction from 15.9mV (4 LSB) to 1.98mV (0.5 LSB), with measured DNL and INL within + 0.5/-0.7 LSB and +/- 1 LSB respectively. Operating at 160 MS/s sampling rate, it achieves 44.9dB SNDR and 49.9dB SFDR for near-Nyquist full-scale inputs, while consuming 0.65 mW, resulting in a figure of merit (FoM) of 28.2 fJ/conversion step.

The parallel multi-wavelength light source plays a critical role in optical input/output (I/O) systems by providing multiple wavelengths to enhance data transmission capacity and flexibility. This study proposes and experimentally demonstrates, to our knowledge, a novel on-chip parallel multi-wavelength light source based on an eight-wavelength distributed feedback (DFB) laser array, an arrayed waveguide grating (AWG), and a Y-branch light power splitter for optical I/O applications. The ac-phase-shifted laser array is designed using the reconstructed equivalent chirp (REC) method for precise wavelength control. The AWG is designed for eight-wavelength multiplexing, while the Y-branches function as output interfaces, supporting 64 channels across eight ports simultaneously. An output power exceeding 6.9 dBm is achieved at each of the eight output ports. Furthermore, the linewidth of the representative wavelength is measured to be 361.5 kHz, and clear 25 Gb/s non-return-to-zero (NRZ) eye diagrams are obtained. The proposed parallel multi-wavelength source scheme offers a compact and promising solution for advancing optical I/O technology.

In this paper, we have developed a novel crystalline metal oxide thin‐film transistor (TFT) that achieves a significant improvement in device mobility and stability. Unlike the conventional amorphous process, the fabrication of crystalline metal oxide TFTs requires special control of the crystallization process. Based on the G4.5 production line, we have specifically optimized the deposition process to obtain a thin film with good large‐area uniformity. Ultimately, through multiple rounds of optimization and fine‐tuning of the device process, we have successfully fabricated crystalline oxide TFT devices with a mobility of 46.2 cm 2 /V·s, a positive bias temperature stress (PBTS) of 0.25 V, and a negative bias temperature stress (NBTIS) of ‐ 1.04 V.

With the development of display technologies, the demand for super‐sized displays is strong increased. To meet the requirement of super‐sized display, the video wall, which can be roughly divided into LCD splicing and MLED splicing, is usually used. For LCD video wall, there are black edges and seams. For MLED splicing, the pitch is large, and cost is high. We combine the LCD and MLED display to form a whole display called MLCD. Compare to the common LCD/MLED splicing display, MLCD can meet the requirement of super‐sized display, and without the grid‐shaped black edge at the same time. Furthermore, in order to improve picture quality, we developed some key technologies to avoid non‐alignment and tearing.