赛灵思

The ambitious performance targets of modern wireless networks, including 6G and Industrial IoT (IIoT) systems, necessitate advanced hardware platforms utilizing millimeter-wave (mmWave) technology. High-frequency signals provide the bandwidth and low latency required for these systems, but rely on beamforming to overcome path loss and exploit channel sparsity. This kind of architecture provides all the specifications needed to build a SLAM (Simultaneous Localization and Mapping) system. This paper presents a dataset based on a validated, high-performance testbed integrating a Xilinx Zynq UltraScale+ RFSoC with a Sivers 60 GHz beamforming front-end. We demonstrate a novel methodology using segment-scrambled, quasi-orthogonal chirp waveforms to perform rapid exhaustive beamspace sampling. The system is integrated with Pynq Linux for real-time control and high-speed waveform upload. We present a high-density spatial dataset consisting of 350 measurement points across a 1.95 m x 3.60 m indoor grid. We exploited the system's ability to scan 63 transmit directions and construct a complete 63x63 beamspace intensity map in 200us. This dataset serves as a benchmark for spatial channel modeling, Digital Twins and Integrated Sensing and Communication (ISAC) research.

Cell placement is such a critical step for chip physical design that it needs many kinds of efforts for improvement. Recently, designs with 2D processing element arrays have become popular primarily due to their deep neural network computing applications. The 2D array regularity is similar to but different from the regularity of conventional datapath designs. To exploit the 2D array regularity, this work develops a new global placement technique built upon RePlAce, the latest state-of-the-art placement framework. Experimental results from various designs show that the proposed technique can reduce half-perimeter wirelength and Steiner tree wirelength by about $6%$ and $12%$, respectively.

Constructing a Trusted Execution Environment (TEE) on Field Programmable Gate Array System on Chip (FPGA-SoC) in Cloud can effectively protect users' private intel-lectual Property (IP) cores. In order to facilitate the wide-spread deployment of FPGA-SoC TEE, this paper proposes an approach for constructing a TPM 2.0-compatible runtime customizable TEE on FPGA-SoC. This approach leverages a user-controllable virtual Trusted Platform Module (vTPM) that integrates sensitive operations specific to FPGA-SoC TEE. It provides TPM 2.0 support for a customizable FPGA-SoC TEE to dynamically measure, deploy, and invoke IP during runtime. Our main contributions include: (i) Propose an FPGA-vTPM architecture that enables the TPM 2.0 specification support for FPGA-SoC TEE; (ii) Explore the utilization of FPGA-vTPM to dynamically measure, deploy, and invoke users' IPs on FPGA-SoC TEE; (iii) Extend the TPM command set to accommodate the sensitive operations of FPGA-SoC TEE, enabling users to perform sensitive tasks in a secure and verifiable manner according to the TPM 2.0 specification. We implement a prototype of TRCTEE on the Xilinx Zynq UltraScale+ MPSoC platform and conducted security analysis and performance evaluations to prove the practicality and enhanced security features of this approach.

The rapid development of artificial intelligence (AI), machine learning, and data-centric computing has significantly amplified the demand for highly efficient on-chip communication topologies in today's accelerator platforms. AI accelerators feature several processing parts, memory hierarchies, tensor engines and special computational units that need to move large amounts of data with low latency and optimal efficiency. Traditional bus-based communication systems cannot provide the bandwidth and scalability requirements of modern AI workloads, particularly deep learning training and inference with large neural network models. This leads to the necessity of Network-on-Chip (NoC) architectures as a vital solution for scalable and high-performance interconnectivity in AI accelerator systems. High-bandwidth NoCs provide efficient packet-based communication across distributed processing nodes, leading to enhanced parallelism, better resource utilization, and improved overall system throughput. The design of an effective NoC for AI accelerator platforms has become an important issue of scalability, communication latency, congestion control, power efficiency, and dependability. More processing cores and memory interfaces make low-latency communication harder to preserve and network traffic congestion harder to avoid. Further, interconnect fabrics with high bandwidths have large power consumption and may limit the temperature for the progress of semiconductor technology. However, the use of NoC in large-scale AI systems is hindered by reliability difficulties such as packet loss, deadlocks, fault tolerance, and traffic imbalance. This paper presents a complete methodology for the design of high-bandwidth Network-on-Chip (NoC) for AI accelerator platforms, focusing on scalable topology selection, adaptive routing algorithms, congestion-aware traffic management, low-power communication techniques, and methods for enhancing dependability. We demonstrate a case study of a practical AI accelerator to explain implementation considerations and performance trade-offs for real AI workloads. Experimental research shows that the proposed methodology may significantly optimize bandwidth utilization, reduce communication latency, alleviate congestion hotspots and enhance energy efficiency compared to typical NoC systems.

SCN2A-related disorders (RDs) are genetic conditions characterized by severe to profound impairments in multiple domains including gross motor function, which could serve as a nonseizure outcome in precision medicine therapy trials. This study evaluated specific properties of the Vineland Adaptive Behavior Scales-3 (VABS3) and other motor assessments for their fitness for use in trials of SCN2A-RDs. Sixty-five families recruited through the FamileSCN2A foundation enrolled their affected children ("participants," 28 female, median age 6.4 years, interquartile range [IQR] 4.1-10.5) in a 1-year, longitudinal study. Assessments were administered at 0 (study entry), 6, and 12 months. Assessments included the VABS3, Adaptive Behavior Assessment System 0-5 years (ABAS), a modified Functional Mobility Scale (FMS), and the Functional Activities Questionnaire-Walking Level (FAQ-WL). The VABS3 composite score (34 [IQR 26-46]) indicated overall adaptive function >4 SDs below the normative mean. Forty percent of participants aged 2 years or older required wheelchairs for home distances, and 28% could not take any steps. The median standardized scores (SSs) for the VABS3 motor domain (20 [IQR 20-32]) and gross motor subdomain (1 [IQR 1-2]) reflected performance at the floor of the measures. Standardized motor scores discriminated poorly among participants with different levels of mobility (FAQ-WL and FMS) and different markers of diseases severity (presence of epilepsy, history of epileptic spasms, number of seizure medications). Cross-sectionally, SSs declined with increasing age. By contrast, raw scores of the VABS3 and ABAS and growth scale values (GSVs) of the VABS3 had relatively little floor effects. They distinguished well between participants based on FAQ-WL and FMS scores and between those with different disease severity markers. Test-retest and inter-rater reliability for all scores were excellent. No motor score changed significantly over time in the longitudinal analyses. Gross motor function in people with SCN2A-RDs is so severely impaired that it cannot be adequately measured with norm-referenced (standardized) scores. GSVs and alternative scoring assessments used out of their intended age range have superior and promising psychometric features in this severely impaired group, and they should be considered in future precision medicine trials for SCN2A-RDs and other similarly severe, rare disorders.