Deterministic Synchronous Multichannel Extension (DSME) is a prominent MAC behavior first introduced in IEEE 802.15.4e supporting deterministic guarantees using its multisuperframe structure. DSME also facilitates techniques like multi-channel and Contention Access Period (CAP) reduction to increase the number of available guaranteed timeslots in a network. However, any tuning of these functionalities in dynamic scenarios is not explored in the standard. In this paper, we present a multisuperframe tuning technique called DynaMO which tunes the CAP reduction and Multisuperframe Order in an effective manner to improve flexibility and scalability, while guaranteeing bounded delay. We also provide simulations to prove that DynaMO with its dynamic tuning feature can offer up to 15--30% reduction in terms of latency in a large DSME network.
Hands-on experience is crucial to truly understanding the principles of operating systems (OS). This paper describes a preemptive, multithreaded embedded OS assigned as a project in a junior-level OS course. It targets the popular 8051 instruction set architecture (ISA) and can run with as little as 128 bytes of RAM and 1 KB of program memory with preemption and synchronization primitives such as semaphores. It is written in C and assembly and compiled using the open-source Small Device C Compiler (SDCC). It runs on the free EdSim51 simulator, which simulates common peripherals such as LCD, keypads, 7-segment LEDs, ADC, and UART all in high fidelity. This course project has received positive feedback from students who took the course.
Industrial process control systems are time-critical systems where reliable communications between sensors and actuators need to be guaranteed within strict deadlines to maintain safe operation of all the components of the system. WirelessHART is the most widely adopted standard which serves as the medium of communication in industrial setups due to its support for Time Division Multiple Access (TDMA) based communication, multiple channels, channel hopping, centralized architecture, redundant routes and avoidance of spatial re-use of channels. However, the communication schedule in WirelessHART network is decided by a centralized network manager at the time of network initialization and the same communication schedule repeats every hyper-period. Due to predictability in the time slots of the communication schedule, these systems are vulnerable to timing attacks which eventually can disrupt the safety of the system. In this work, we present a moving target defense mechanism, the SlotSwapper, which uses schedule randomization techniques to randomize the time slots over a hyper-period schedule, while still preserving all the feasibility constraints of a real-time WirelessHART network and makes the schedule uncertain every hyper-period. We tested the feasibility of the generated schedules on random topologies with 100 simulated motes in Cooja simulator. We use schedule entropy to measure the confidentiality of our algorithm in terms of randomness in the time slots of the generated schedules.
Virtualization is the main building block of many architectures and systems from embedded computing to large scale data-centers. Managing efficiently computing resources and their power consumption becomes fundamental to optimize the performance of the workloads running on those systems, however, hardware tools like Intel RAPL can only introduce power caps without considering performance. This paper presents a performance-aware power capping orchestrator for the Xen hypervisor. The tool exploits hybrid power management techniques to minimize power consumption respecting a given SLA, leveraging RAPL and overcoming its limitations. Experimental evaluation shows that the proposed approach guarantees good results for almost all the analyzed benchmarks (e.g. CPU-, memory- and IO-bound).
Some of the most recent applications and services revolve around the analysis of time-series, which generally exhibits chaotic characteristics. This behavior brought back the necessity to simplify their representation to discover meaningful patterns and extract information efficiently. Furthermore, recent trends show how computation is moving back from the Cloud to the Edge of network, meaning that algorithms should be compatible with low-power embedded devices. A family of methods called Symbolic Analysis (SA) tries to solve this issue, reducing the dimensionality of the original data in a set of symbolic words and providing distance metrics for the obtained symbols. However, SA is usually implemented using application-specific tools, which are not easily adaptable, or mathematical environments (e.g. R, Julia) that do not ensure portability, or that require additional work to maximize computing performance. We propose here SAGe: a code generation tool that helps the user to prototype efficient and portable code, starting from a high-level representation of SA requirements. Other than exploiting similarities between SA pipelines, SAGe employs general code templates to build and deploy the code on different architectures, such as embedded devices, microcontrollers, and FPGAs. Preliminary results show a speedup up to 223x against Python implementations running on an x86 desktop machine and a notable increase in computational efficiency on a reconfigurable device.
Hands-on experience is crucial to truly understanding the principles of operating systems (OS). This paper describes a preemptive, multithreaded embedded OS assigned as a project in a junior-level OS course. It targets the popular 8051 instruction set architecture (ISA) and can run with as little as 128 bytes of RAM and 1 KB of program memory with preemption and synchronization primitives such as semaphores. It is written in C and assembly and compiled using the open-source Small Device C Compiler (SDCC). It runs on the free EdSim51 simulator, which simulates common peripherals such as LCD, keypads, 7-segment LEDs, ADC, and UART all in high fidelity. This course project has received positive feedback from students who took the course.
In a quest for making FPGA technology more accessible to the software community, Xilinx recently released PYNQ, a framework for Zynq that relies on Python and overlays to ease the integration of functionalities of the programmable logic into applications. In this work we build upon this framework to enable transparent hardware acceleration for scientific computations for Zynq. We do so by providing a custom NumPy library designed for PYNQ, as it is the de-facto scientific library for Python. We then demonstrate the effectiveness of the proposed approach on a biomedical use case involving the extraction of features from the Electroencephalography (EEG).
ARM big.LITTLE architectures are spreading more and more in the mobile world thanks to their power-saving capabilities due to the use of two ISA-compatible islands, one focusing on energy efficiency and the other one on computational power. This architecture makes the problem of energy-aware task scheduling particularly challenging, due to the number of variables to take into account and the need for having lightweight mechanisms that can be readily computed in an operating system kernel scheduler. This paper presents a novel task scheduler for big.LITTLE platforms, combining the well-known Constant Bandwidth Server algorithm with a power-aware per-job migration policy. This achieves real-time adaptation of the CPU islands' frequencies based on the individual cores' overall utilization, as available in the scheduler thanks to the use of the resource reservation paradigm. Preliminary results obtained by simulations based on modifications to the open-source RTSim tool show that the proposed technique is able to achieve interesting performance/energy trade-offs.
In the last few years Internet of Things (IoT) applications are moving from the cloud-sensor paradigm to a more variegated structure where IoT nodes interact with an intermediate fog computing layer. To enable compute-intensive tasks to be executed near the source of the data, fog computing nodes should provide enough performance and be sufficiently energy efficient to run on the field. Within this context, embedded Field Programmable Gate Array (FPGA) can be used to improve the performance per Watt ratio of fog computing nodes. In this paper we present Fog Acceleration through Reconigurable Devices (FARD), a distributed system that exploits FPGAs to accelerate compute-intensive tasks in fog computing applications. FARD is able to efficiently run distributed fog applications thanks to a well-defined application structure, a per-application isolated network overlay and thanks to the acceleration of tasks. Results show energy efficiency improvements while efficiently enabling cooperation across fog nodes.
This paper presents Real-Time Network-on-chip-based architecture Analysis and Simulation tool (ReTiNAS), with a special focus on real-time communications. It allows fast and precise exploration of real-time design choices onto NoC architectures. ReTiNAS is an event-based simulator written in Python. It implements different real-time communication protocols and tracks the communications within the NoC at cycle level. Its modularity allows activating and deactivating different NoC components and easily extending the implemented protocols for more customized simulations and analysis. Further, we use ReTiNAS to perform a comparative study of analysis and simulation for different communication protocols using a wide set of synthetic experiments.
Intermittently-powered embedded devices (IPDs) are getting wide-spread attention these days. However, running periodic real-time tasks on these devices remains a challenging problem due to the lack of support for data freshness guarantees, timekeeping, and schedulability analysis. Especially, while many sensing tasks require long atomic operations for data acquisition from sensors, most prior work on IPDs assumes compute-only workloads and disregards such sensor operations. In this paper, we present a new energy scheduling scheme to execute periodic real-time tasks with atomic sensing operations. Our scheme keeps track of time and ensures the periodic execution of sensing tasks while efficiently utilizing intermittent power sources. We provide schedulability analysis to determine if a task is schedulable in a given charging setup, and extend this idea for scheduling multiple tasks. As a proof-of-concept, we design a custom programmable RFID tag device, called R'tag, and demonstrate the effectiveness of our proposed techniques in a realistic sensing application. We compare the baseline approach and the proposed scheme in both simulation and real platforms. Experimental results show that the proposed method outperforms the baseline approach in terms of task scheduling, timekeeping, and periodic sensing.
Deterministic Synchronous Multichannel Extension (DSME) is a prominent MAC behavior first introduced in IEEE 802.15.4e supporting deterministic guarantees using its multisuperframe structure. DSME also facilitates techniques like multi-channel and Contention Access Period (CAP) reduction to increase the number of available guaranteed timeslots in a network. However, any tuning of these functionalities in dynamic scenarios is not explored in the standard. In this paper, we present a multisuperframe tuning technique called DynaMO which tunes the CAP reduction and Multisuperframe Order in an effective manner to improve flexibility and scalability, while guaranteeing bounded delay. We also provide simulations to prove that DynaMO with its dynamic tuning feature can offer up to 15--30% reduction in terms of latency in a large DSME network.
As system complexity grows, embedded operating systems increasingly face the challenge to adhere to various non-functional constraints, such as response times and power limits. These requirements sometimes contradict and, often, no solution satisfies all constraints under all conditions. Changes in environmental conditions, application-level requirements, and user response time expectation hence demand for system-wide adaptions to resource management. We find that process synchronization constitutes a simple yet effective leverage point to balance between timing-related and energy-related constraints. This paper presents Earl, an implementation of reconfigurable locks in Linux that enables seamless transitions between high-performance and low-power operating modes.
Industrial process control systems are time-critical systems where reliable communications between sensors and actuators need to be guaranteed within strict deadlines to maintain safe operation of all the components of the system. WirelessHART is the most widely adopted standard which serve as the medium of communication in industrial setups due to its support for Time Division Multiple Access (TDMA)based communication, multiple channels, channel hopping, centralized architecture, redundant routes and avoidance of spatial re-use of channels. However, the communication schedule in WirelessHART network is decided by a centralized network manager at the time of network initialization and the same communication schedule repeats every hyper-period. Due to predictability in the time slots of the communication schedule, these systems are vulnerable to timing attacks which eventually can disrupt the safety of the system. In this work, we present a moving target defense mechanism, the SlotSwapper, which uses schedule randomization techniques to randomize the time slots over a hyper-period schedule, while still preserving all the feasibility constraints of a real-time WirelessHART network and makes the schedule uncertain every hyper-period. We tested the feasibility of the generated schedules on random topologies with 100 simulated motes in Cooja simulator. We use schedule entropy to measure the confidentiality of our algorithm in terms of randomness in the time slots of the generated schedules.
Deterministic Synchronous Multichannel Extension (DSME) is a prominent MAC behavior first introduced in IEEE 802.15.4e supporting deterministic guarantees using its multisuperframe structure. DSME also facilitates techniques like multi-channel and Contention Access Period (CAP) reduction to increase the number of available guaranteed timeslots in a network. However, any tuning of these functionalities in dynamic scenarios is not explored in the standard. In this paper, we present a multisuperframe tuning technique called DynaMO which tunes the CAP reduction and Multisuperframe Order in an effective manner to improve flexibility and scalability, while guaranteeing bounded delay. We also provide simulations to prove that DynaMO with its dynamic tuning feature can offer up to 15--30% reduction in terms of latency in a large DSME network.
This paper presents our preliminary results on development of a Cognitive assistant system for Emergency Medical Services (CognitiveEMS) that aims to improve situational awareness and safety of first responders. CognitiveEMS integrates a suite of smart wearable sensors, devices, and analytics for real-time collection and analysis of in-situ data from incident scene and delivering dynamic data-driven insights to responders on the most effective response actions to take. We present the overall architecture of CognitiveEMS pipeline for processing information collected from the responder, which includes stages for converting speech to text, extracting medical and EMS protocol specific concepts, and modeling and execution of an EMS protocol. The performance of the pipeline is evaluated in both noise-free and noisy incident environments. The experiments are conducted using two types of publicly-available real EMS data: short radio calls and post-incident patient care reports. Three different noise profiles are considered for simulating the noisy environments: cafeteria, people talking, and emergency sirens. Noise was artificially added at 3 intensity levels of low, medium, and high to pre-recorded audio data. The results show that the i) state-of-the-art speech recognition tools such as Google Speech API are quite robust to low and medium noise intensities; ii) in the presence of high noise levels, the overall recall rate in medical concept annotation is reduced; and iii) the effect of noise often propagates to the final decision making stage and results in generating misleading feedback to responders.
Deterministic Synchronous Multichannel Extension (DSME) is a prominent MAC behavior first introduced in IEEE 802.15.4e. It can avail deterministic and best effort Service using its multisuperframe structure. RPL is a routing protocol for wireless networks with low power consumption and generally susceptible to packet loss. These two standards were designed independently but with the common objective to satisfy the requirements of IoT devices in terms of limited energy, reliability and determinism. A combination of these two protocols can integrate real-time QoS demanding and large-scale IoT networks. In this paper, we propose a new multi-channel, multi-timeslot scheduling algorithm called Symphony that provides QoS efficient schedules in DSME networks. In this paper we provide analytical and simulation based delay analysis for our approach against some state of the art algorithms. In this work, we show that integrating routing with DSME can improve reliability by 40% and by using Symphony, we can reduce the network delay by 10--20% against the state of the art algorithms.
This paper presents our preliminary results on development of a Cognitive assistant system for Emergency Medical Services (CognitiveEMS) that aims to improve situational awareness and safety of first responders. CognitiveEMS integrates a suite of smart wearable sensors, devices, and analytics for real-time collection and analysis of in-situ data from incident scene and delivering dynamic data-driven insights to responders on the most effective response actions to take. We present the overall architecture of CognitiveEMS pipeline for processing information collected from the responder, which includes stages for converting speech to text, extracting medical and EMS protocol specific concepts, and modeling and execution of an EMS protocol. The performance of the pipeline is evaluated in both noise-free and noisy incident environments. The experiments are conducted using two types of publicly-available real EMS data: short radio calls and post-incident patient care reports. Three different noise profiles are considered for simulating the noisy environments: cafeteria, people talking, and emergency sirens. Noise was artificially added at 3 intensity levels of low, medium, and high to pre-recorded audio data. The results show that the i) state-of-the-art speech recognition tools such as Google Speech API are quite robust to low and medium noise intensities; ii) in the presence of high noise levels, the overall recall rate in medical concept annotation is reduced; and iii) the effect of noise often propagates to the final decision making stage and results in generating misleading feedback to responders.
A carefully designed routing synthesis can help system designers achieve a better load balancing in TSN-based networks and avoid congestion. To this end purpose, this work proposes two heuristics referred to as (1) LB-DRR, which aims at achieving a better load balancing and compute as much disjoint routing paths as possible for each replicated flow; and (2) CR-DRR, which recomputes paths for time-sensitive flows in congestion situations. Extensive simulations demonstrate that the proposed approach outperforms the classical Shortest Path (SPA) and the weighted Equal Cost Multi-path (wt-ECMP) algorithms in terms of the maximum load transmitted on a link by more than 70% and 20%, respectively.
Fog computing aims to support novel real-time applications by extending cloud resources to the network edge. This technology is highly heterogeneous and comprises a wide variety of devices interconnected through the so-called fog layer. Compared to traditional cloud infrastructure, fog presents more varied reliability challenges, due to its constrained resources and mobility of nodes. This paper summarizes current research efforts on fault tolerance and dependability in fog computing and identifies less investigated open problems, which constitute interesting research directions to make fogs more dependable.
