Pattern matching based on Regular Expressions (REs) is a pervasive and challenging computational kernel used in several applications to identify critical information in a data stream. Due to the sequential data dependency of REs and the increasing data volume growth, hardware acceleration is gaining attention to address the limitation of general-purpose architectures. RE-oriented Domain-Specific Architectures (DSAs) combine the flexibility of translating REs into binary code with the efficiency of a specialized architecture, filling the gap between frozen hardware accelerators and the versatility of CPUs/GPUs. However, existing DSAs focus mainly on the efficiency execution challenge while missing the optimization opportunities that a structured compilation infrastructure can provide. This paper proposes a RE-tailored multi-level intermediate representation strategy embodied by the MLIR framework at the compiler level to exploit different abstraction optimizations via two domain-specific dialects, one targeting the abstract representation of REs and the other targeting the underlying domain-specific ISA. Moreover, this paper proposes a novel architectural organization of an open-source state-of-the-art DSA to maximize the parallelization capabilities. Overall, the proposed approach significantly improves execution time by up to 2.26×, energy efficiency by up to 2.30×, and resource usage.

Regular Expression (RE) matching enables the identification of patterns in datastreams of heterogeneous fields ranging from proteomics to computer security. These scenarios require massive data analysis that, combined with the high data dependency of the REs, leads to long computational times and high energy consumption. Currently, RE engines rely on either (1) flexibility in run-time RE changes and broad operators support impairing performance or (2) fixed high-performing accelerators implementing few simple RE operators. To overcome these limitations, we propose ALVEARE: a hardware-software approach combining a Domain-Specific Language (DSL) with an embedded Domain-Specific Architecture. We exploit REs as a DSL by translating them into flexible executables through our RISC-based Instruction Set Architecture that expresses from simple to advanced primitives. Then, we design a speculationbased microarchitecture to execute real benchmarks efficiently. ALVEARE provides RE-domain flexibility and broad operators' support and achieves up to 34x speedup and 57x energy efficiency improvements against the state-of-the-art RE2 and Bluefield DPU 2 with its RE accelerator.

Regular Expressions (REs) matching is crucial to identify strings exhibiting certain morphological properties in a data stream, resulting paramount in contexts such as deep packet inspection in computer security and genome analysis in bioinformatics. Yet, due to their intrinsic data-dependence characteristics, REs represent a complex computational kernel, and numerous solutions investigate pattern-matching efficiency in different directions. However, most of them lack a comprehensive ruleset optimization approach to truly push the pattern matching performance when considering multiple REs together. Thus, exploiting REs morphological similarities within the same dataset allows memory reduction when storing the patterns and drastically improves the dataset-matching throughput. Based on this observation, we propose the Multi-RE Finite State Automata (MFSA) that extends the Finite State Automata (FSA) model to improve REs parallelization by leveraging similarities within a specific application ruleset. We design a multi-level compilation framework to manage REs merging and optimization to produce MFSA(s). Furthermore, we extend iNFAnt algorithm for MFSAs execution with the novel iMFAnt engine. Our evaluation investigates the MFSA size-reduction impact and the execution throughput compared with the one of multiple FSA in both single-and multi-threaded configurations. This approach shows an average 71.95% compression in terms of states, introducing limited compilation time overhead. Besides, best iMFAnt achieves a geomean $5.99\times$ throughput improvement and $4.05\times$ speedup against single and multiple parallel FSAs.

The pervasiveness of embedded systems across edge and connected devices is challenging their design, as sharing data securely via AES encryption is computationally intensive. This work proposes POCA, an FPGA-accelerated HW/SW library that performs AES cryptographic primitives with different modes and the most used key sizes. The HW/SW approach of POCA showcases the benefits of accelerated cryptographic primitives and the flexibility of a unified platform interface across different embedded systems by exploiting the Python PYNQ framework. POCA matches the multicore ARM crypto extensions on an Ultrascale+ ZU3EG while overwhelming SW performance.

Regular Expressions (REs) are a computational kernel widely used for finding patterns in data in compute-intensive tasks such as genomic markers research, signature-based detection, and database query. Although flexible on the set of searched REs, software-based solutions cannot fulfill latency or throughput requirements to analyze massive data volumes at a given power budget. For this reason, many approaches exploit hardware accelerators as an offloading engine for REs matching. Indeed, various solutions rely on FPGA reconfigurability to embed automata into the reconfigurable fabric. However, this approach leads to time-consuming updates of the REs to search. This work exploits REs as sequences of basic instructions and builds a Domain-Specific Architecture (DSA), called TiReX, for RE matching on FPGAs. Our approach enables the user to change the desired RE at run-time, providing software programmability, flexibility, and specialized hardware mechanisms. Our DSA delivers performance in line with other state-of-the-art hardware approaches, while providing remarkable flexibility and we underline the importance of energy efficiency for these computations. We compared with multiple state-of-the-art software obtaining remarkable performance while achieving noticeable results with a better energy efficiency that ranges from 3× to 490× with our multi-core.

The number of low-power Internet-connected de-vices has significantly increased in the last decade, mainly due to the proliferation of smartphones and IoT devices. However, strict power constraints and high computational demands in conjunction with the end of fundamental computer science laws have introduced new hardware and software design challenges. Domain-specialized FPGA-based hardware accelerators are a promising approach to overcoming these challenges, providing an excellent tradeoff between performance and flexibility in accelerating complex tasks. However, the required competencies to design hardware accelerators strongly limit their adoption. This paper presents a co-design approach describing the general steps to take while developing a hardware-accelerated kernel using the PYNQ platform for software implementation. We applied the proposed approach using the AES-CTR cipher as a case study, one of the most common algorithms for secure communications and data encryption, showing the benefits that hardware acceleration can bring in constrained scenarios. The reported execution results of our approach demonstrate that exploiting hardware acceleration brings a remarkable execution speed-up while keeping the design complexity low.

The continuous growth of data pushes novel and efficient approaches for information retrieval. In this context, Regular Expression (RE) matching is widely employed and represents a relevant computational kernel that carries control-and memory-related issues. Among the several solutions to relieve these burdens, accelerators seem a promising alternative to general-purpose systems. However, state-of-the-art benchmarking presents a highly fragmented scenario without consensus on the approach and lacks an open-source strategy. Therefore, to fairly characterize existing execution engines, this work presents YARB, an open benchmarking methodology. It builds upon literature solutions, a comprehensive approach, and an in-depth characterization of heterogeneous systems. Moreover, YARB's openness will enable future integrations and engines comparison.

In Cyber-Physical Systems (CPS) and Internet of Things (IoT) systems, many high-demanding applications are cut off due to the limited computational resources and the necessity to keep energy consumption as low as possible. For instance, pattern matching is a complex kernel for many essential applications, such as computer security, and the high computational and energy requirements can strongly limit its use. This paper proposes a system that combines an efficient Domain-Specific Architecture for Regular Expressions to enable host-based intrusion detection systems on edge FPGA-based devices. We demonstrate comparable execution times and remarkable energy efficiency improvements compared to a Raspberry PI. Moreover, our work aims to facilitate complex tasks offloading (such as security ones) in constrained scenarios while keeping a low energy profile and comparable performance.

Sleep disorders are a significant public health concern, affecting approximately 30 % of adults. These conditions are associated with various health issues, including hyperac-tivity disorder, diabetes, hypertension, cardiovascular diseases, and obesity. Monitoring the resting environment is paramount to taking the first step toward getting a good night's sleep. Technological advances have recently allowed the development of non-invasive sleep monitoring systems, essential to minimize interferences with the monitored sleep quality. Such systems can improve individuals' sleep quality by identifying potential sleep- disturbing elements in private bedrooms. In this paper, we present a non-invasive sleep environment monitoring system based on Arduino, which acquires data on main environmental factors affecting sleep quality and duration, such as noise, light, and room temperature. The data from the sensors are processed and analyzed using the Arduino boards in conjunction with a tailored Google platform, providing real-time monitoring of the sleep environment. By allowing individuals to monitor their sleep environment, the proposed system aims to promote awareness and encourage healthy sleep practices, improving overall health outcomes. In conclusion, the non-invasive sleep environment monitoring system presented in this paper offers a promising approach to addressing the issue of sleep disorders. Its simple design and user-friendly interface make it an accessible tool for non-expert users looking to optimize their sleep environment and improve their sleep quality. We believe that this system has the potential to contribute significantly to the field of sleep health.

Pairwise sequence alignment is a fundamental step for many genomics and molecular biology applications. Given the quadratic time complexity of alignment algorithms, the community demands innovative, fast, and efficient techniques to perform this task. Furthermore, general-purpose architectures lack the necessary performance to address the computational load of these algorithms. In this context, we present the first open-source FPGA implementation of the popular KSW2z algorithm employed by minimap2. Our design also implements the $Z- \mathbf{drop}$ heuristic and banded alignment as the original software to further reduce the processing time if needed. The proposed multi-core accelerator achieves up to $\mathbf{7.70}\times$ improvement in speedup and $\mathbf{20.07}\times$ in energy efficiency compared to the multi-threaded software implementation run on a Xeon Platinum 8167M processor.

For the last two years, the world has been fighting an invisible enemy: COVID-19 (coronavirus). The spreading of this virus caused an unprecedented pandemic, bringing out some critical health system issues due to overcrowded hospitals and undersized medical personnel compared to the number of infected. Indeed, in this context, health facilities have proven inadequate in treating COVID-19 patients who were in quarantine at home, leading to overcrowded hospitals. An efficient home monitoring system would have reserved hospital beds for patients in severe conditions while, at the same time, doctors would have followed up on patients who had mild disease symptoms remotely. Unfortunately, the development of telemedicine was not enough; devices were not user-friendly and had insufficient memory to guarantee daily data storage. ROH-BOT is an IoT device that allows real-time contact with the doctor, tracking the patient’s vital values, and registers the critical parameters that characterize the specific disease. It also allows quick contact with a trusted third person due to its association with a Telegram bot. Moreover, thanks to its user-friendly characteristics, ROH-BOT increases the growing digitalization in the medical field and the democratization of medical technology. In this way, ROH-BOT aims to solve the difficulties related to home monitoring relieved during the pandemic.

This paper aims to show how a low-cost Brain-Computer Interface (BCI) device can effectively and accurately collect brain signals to control a simple machine or toy, using a versatile methodology that can adapt to different use cases. We used the EMOTIV Insight headset in conjunction with EMOTIV’s software tools to interpret brain activity and an Arduino microcontroller to handle interfacing between the computer and the controlled device. This study evaluates the feasibility of moving a car on a slot car track using the focus levels of the user as a reference. Comparing the concentration levels achieved while completing a logic-based puzzle with those reached when focusing on the car suggests the viability of this approach for the task since users can effectively and consciously control their attention level. This approach offers flexibility to adapt a wide range of appliances or toys without reliance on the manufacturer to provide accessibility, offering to people with severe physical disabilities new opportunities to interact with the world. The proposed methodology allows to conduct testing inexpensively and effectively, helping discern the best approach for a customized product before manufacturing it.

In a quest for making FPGA technology more accessible to the software community, Xilinx recently released PYNQ, a framework for Zynq that relies on Python and overlays to ease the integration of functionalities of the programmable logic into applications. In this work we build upon this framework to enable transparent hardware acceleration for scientific computations for Zynq. We do so by providing a custom NumPy library designed for PYNQ, as it is the de-facto scientific library for Python. We then demonstrate the effectiveness of the proposed approach on a biomedical use case involving the extraction of features from the Electroencephalography (EEG).

The human brain is a complex system consisting of interconnections between different neurons and regions creating networks, known as Brain Networks. Of particular relevance in this context are Resting State Networks (RSNs), which are synchronous fluctuations between spatially distinct regions, occurring in the absence of a task or stimulus. Neuroscientists have identified alterations in RSNs in many neurodegenerative diseases, thus a long-term analysis of them is fundamental to monitor alterations in brain functional connectivity. However, the statistical tools in charge of analyzing RSNs currently fail in reaching significant levels of throughput, due to the huge amount of data to process. For this reason, this paper presents a hardware acceleration on FPGA design of the Independent Component Analysis (ICA), a state-of-the-art statistical method for RSNs recognition, in order to accelerate the data analysis process. We evaluated and deployed our implementation on Amazon F1 instances. The experimental evaluation shows that our hardware implementation is able to outperform GIFT, one of the most commonly used tools to identify RSNs, by a factor of 5×.