International Conference on Embedded Software

ACM Reference Format: Samarjit Chakraborty1 Jingtong Hu2 Qi Zhu3. 2025. Tutorial: Design Automation for ML-enabled Cyber-Physical Systems: From Verification to Synthesis. In International Conference on Embedded Software (EMSOFT ‘25), September 28-October 3, 2025, Taipei, Taiwan. ACM, New York, NY, USA, 2 pages. https://doi.org/10.1145/3742874.3758336

Tiny battery-free devices running deep neural networks (DNNs) embody intermittent TinyML, a paradigm at the intersection of intermittent computing and deep learning, bringing sustainable intelligence to the extreme edge. This paper, as an overview of a special session at Embedded Systems Week (ESWEEK) 2025, presents four tales from diverse research backgrounds, sharing experiences in addressing unique challenges of efficient and reliable DNN inference despite the intermittent nature of ambient power. The first explores enhancing inference engines for efficient progress accumulation in hardware-accelerated intermittent inference and designing networks tailored for such execution. The second investigates computationally light, adaptive algorithms for faster, energy-efficient inference, and emerging computing-in-memory architectures for power failure resiliency. The third addresses battery-free networking, focusing on timely neighbor discovery and maintaining synchronization despite spatio-temporal energy dynamics across nodes. The fourth leverages modern nonvolatile memory fault behavior and DNN robustness to save energy without significant accuracy loss, with applicability to intermittent inference on nano-satellites. Collectively, these early efforts advance intermittent TinyML research and promote future cross-domain collaboration to tackle open challenges.

On-device AI enables real-time, privacy-preserving inference but remains constrained by the limited resources of edge devices. To address these constraints, static optimization techniques are employed to reduce model complexity, yet they often fail to handle dynamic challenges such as bursty input streams. We propose pipelined DNN inference, where a model is partitioned into sub-models that execute concurrently across heterogeneous accelerators. We examine the supporting software stack, introduce a model slicer that ensures correct partitioning, and present a multithreaded inference architecture that overlaps pipeline stages to maintain stable throughput even under surges in input rate.

Ensuring predictable and deterministic behavior in distributed cyber-physical systems (CPS) is essential for guaranteeing safety, reliability, and real-time behavior. However, achieving this predictability is challenging due to network uncertainties, asynchronous execution, and complex timing interactions. This manuscript is based on a special session at Embedded Systems Week (ESWeek) 2025, which brings together experts to explore in four presentations how this uncertainty can be addressed and how to introduce additional determinism into the system to achieve predictable timing behavior in distributed CPS. We begin by exploring cornerstones of timing analysis techniques to provide end-to-end latency guarantees for distributed systems (Chen and Gunzel). Next, we discuss design strategies for meeting timing constraints, focusing on how system parameters influence cause-effect chains and how these parameters can be tuned to ensure predictable behavior in industrial automation settings (Dasari and Becker). We then turn to approaches to achieve more predictable system behavior. To that end, we examine deterministic semantic models for distributed systems that enable the design of robust and fault-tolerant systems (Lee). Finally, we discuss how solving constraints for scheduling cause-effect chains can be used to enforce strict timing guarantees and improve predictability (Bourke).

Federated learning enables decentralized training without sharing raw data, making it suitable for privacy aware applications. However, its performance often degrades in real settings due to unknown and diverse data differences among clients. While many mitigation strategies have been proposed, they typically assume prior knowledge of the imbalance type, such as feature variation, label bias, or data quantity differences, which is unrealistic in practice. This paper addresses the overlooked problem of identifying the main type of data imbalance. We propose a method called Machine Learning based Non IID Estimator, which classifies the imbalance type by analyzing trained client models without accessing any raw data. Similarity matrices computed from model parameters are used to train standard classifiers. Evaluations on the MNIST dataset under controlled imbalance settings show that the proposed method achieves perfect classification accuracy with lightweight models. This highlights the potential of distribution type estimation as a key step toward more robust and efficient federated systems.

This article provides an overview of the Quest real-time operating system (RTOS) and the Quest-V partitioning hypervisor. We summarize the system features and requirements to use the Quest software development kit (SDK). The SDK is capable of prototyping systems combining one or more instances of Quest with legacy services from a Yocto Linux guest. Secure shared memory channels provide the means to build secure and predictable systems of systems.

Hybrid systems are mostly modelled, simulated, and verified in the time domain by computer scientists. Engineers, however, use both frequency and time domain modelling due to their distinct advantages. For example, frequency domain modelling is better suited for control systems, using features such as spectra of the signal. Considering this, we introduce, for the first time, a formal model called frequency automata for hybrid systems modelling and simulation, which are represented in combined time and frequency domains. We propose a sound translation from Hybrid Automata (HA) to Frequency Automata (FA). We also develop a numerical simulator for FA and compare it with the performance of HA. Our approach provides precise level crossing detection and efficient simulation of hybrid systems. We provide empirical results comparing simulation of HA via its translation to FA and its simulation via Matlab Simulink/Stateflow. The results show clear superiority of the proposed technique with the execution times of the proposed technique 118x to 1129x faster compared to Simulink/Stateflow. Moreover, we also observe that the proposed technique is able to detect level crossing with complex guards (including equality), which Simulink/Stateflow fail.

Multicore processor architectures facilitate the integration of applications with different real-time and security requirements. We propose a mixed-criticality system relying on hardware-assisted virtualization that not only shares CPU and memory resources, but also an Ethernet Time-Sensitive Networking (TSN) interface, between applications, taking into account their Quality of Service (QoS) and security requirements. This paper shows how TSN network features can be efficiently exploited in industrial and automotive mixed-criticality systems.

The order in which compiler optimization passes are applied has a significant impact on program performance. However, widely used compiler optimization options use handpicked sets of optimization passes, optimized for specific benchmarks. In this paper, we propose an ensemble reinforcement learning (RL) model that optimizes LLVM transform passes sequence to reduce the runtime memory profile, which is an important consideration in resource-constrained embedded systems. We developed an LLVM intermediate representation (IR) analysis pass to extract static program features. The extracted features are processed with PCA for dimension reduction. We also generated datasets using a random program generator, and clustered them according to the PCA results of their extracted features. The ensemble RL model was trained on each clustered dataset. Experiments showed that the proposed model reduced 37% more memory profile than the standard optimization option.

The resource constraints of MCU-based platforms limits their ability to utilize high-performance accelerators such as GPUs or servers, mainly due to insufficient resources for ML applications. Currently, solutions utilizing accelerators connected as peripherals to the on-chip bus of microcontroller units (MCUs) are being proposed. We define this approach as a Micro-Accelerator (MA). Due to the necessity of connecting the MA to the MCU core and the on-chip bus within the chip, conducting a iterative full system evaluation of the embedded software that drives the MA poses significant challenges. To address this challenge, we propose a framework that enables rapid prototyping of custom-designed MA and facilitates profiling of its acceleration performance. Experimental results evaluating the performance of the MA for two tiny machine learning (TinyML) applications within the proposed framework demonstrate a cycle latency reduction of 84.32% and 61.32% compared to a general machine learning framework, respectively.

This paper presents a programming language for the design and implementation of reactive embedded applications. The language is compiled to hardware descriptions for reconfiguring Field-Programmable Gate Arrays (FPGAs) using logic synthesis toolchains. It features synchronous semantics for fine-grained control on timing and parallelism in the applications. This enables interactions with physical I/Os to be safely composed with algorithms.

While the mixed-criticality (MC) approach is naturally suited for multi-processor (or multi-core) systems, scheduling MC tasks on these platforms is much more complex than in the non-MC case. Here, we improve one of the few approaches that explicitly consider criticality information in scheduling the bus access by allowing a more flexible time allocation to the tasks.

Unishyper is a reliable Rust-based unikernel with good performance for embedded scenarios. It relies on Rust Features to enable customization at fine granularity. To achieve high reliability, Unishyper makes full use of the Rust language features to reduce memory safety bugs, ensure safe resource management, and achieve fault handling and recovery. Finally, Unishyper achieves high performance through safe multi-threading model as well as the single-privilege-level and single-address-space design.

Complex edge systems are often structured with service-oriented architectures. Different communications stacks such as MQTT, DDS, or Zenoh are used, hindering reuse of service implementations across systems. One emerging solution for deploying such services is WebAssembly, which enables platform-independent, secure, and low-overhead execution. We propose a concept for integrating Web-Assembly modules into microservice-based architectures using a specialized runtime. This runtime manages the communication between the WebAssembly module and other parts of the system. The runtime for integration of WebAssembly addresses the challenge of reusing service implementations across systems with different communication protocols. At the same time, this provides isolated, safe and secure execution. Both capabilities are central to service-oriented edge systems.

Rendering redundancy consumes a lot of computing resources in mobile devices. Eliminating redundancy can effectively improve system energy efficiency. However, as the premise of redundancy elimination, the existing redundancy identification methods affect the final performance because of the excessive cost. In this article, we propose the CLERR: a high-performance cross-layer method for eliminating rendering redundancy. CLERR decomposes the redundancy detection process into two collaborative steps, thereby reducing detection overhead. The proposed method is compatible with the mainstream Android 12 system. Experimental results indicate that the method can reduce frame drop rates by 14.5% and save SOC energy by 5.1%.

Several quantitative semantics of temporal logics have been investigated recently. We propose a general form to model those quantitative semantics, establish requirements for soundness, and evaluate the framework on a few examples.

One key technical challenge in the age of autonomous machines is the programming of autonomous machines, which demands the synergy across multiple domains, including fundamental computer science, computer architecture, and robotics, and requires expertise from both academia and industry. This paper discusses the programming theory and practices tied to producing real-life autonomous machines, and covers aspects from high-level concepts down to low-level code generation in the context of specific functional requirements, performance expectation, and implementation constraints of autonomous machines.

The way how automotive software is developed has rapidly evolved with the introduction of heterogeneous hardware/software architectures. Nevertheless, the requirement for deterministic behavior of safety-critical cause-effect chains persists unchanged. As a side effect of the shared platform, complex dependencies between critical and non-critical functions arise, demanding a model-based approach to handle time determinism throughout the design process. Limited to the scope of a single component, the Logical Execution Time (LET) paradigm provides such an abstraction of the runtime behavior. It has been successfully introduced in AUTOSAR to mitigate the design complexity, ensure a deterministic timing behavior and facilitate a lock-free communication. This paper discusses how the scope of LET can be extended to the system level, enabling an efficient design of distributed AUTOSAR software, where robustness towards platform changes plays a key role. System-Level Logical Execution Time (SL-LET) is currently in the process of AUTOSAR standardization, supported by a joint group of industry and academic partners.