The rapid development of integrated circuit (IC) technology, driven by the growing demand for Internet of Things (IoT) devices, cloud computing, and cyber-physical systems, has introduced significant challenges in the design and verification of modern System-on-Chip (SoC) systems. Contemporary SoCs, whether used in desktops or servers, are extremely complex with billions of transistors and often use mixed-core technologies. Designing complex SoCs in modern technologies faces issues in scalability, security, verification, and design optimization, especially as the industry transitions to chipset-based architectures. In this work, we explore the potential of deep learning and generative Artificial Intelligence (AI) to address these challenges, focusing on applications in Register Transfer Level (RTL) code generation, design automation, hardware security, and verification. In this work, we review the state-of-the-art in AI-driven Electronic Design Automation (EDA) tools, examining both open source and commercial platforms that have integrated AI to enhance design efficiency and performance. The work focuses on AI’s role in optimizing power, performance, and area (PPA) metrics, as well as improving hardware security by mitigating threats such as hardware Trojans. In addition, we discuss the implications of adopting AI in SoC workflows and its transformative potential in democratizing hardware design.
This survey explores the application of Large Language Models (LLMs) in Electronic Design Automation (EDA), covering their roles as both assistants and autonomous agents. We review current research and practical implementations where LLMs are utilized for tasks such as question answering, script generation, and automated design processes. This work highlights the benefits of LLMs, including enhanced productivity and innovation, while also addressing challenges like accuracy and integration with traditional EDA tools. Furthermore, we discuss the evolution from LLMs as supportive assistants to more sophisticated agents capable of handling complex EDA workflows. This work aims to provide a comprehensive overview and guide future advancements in the integration of LLMs within the EDA domain.
The ever-growing popularity of large language models (LLMs) has resulted in their increasing adoption for hardware design and verification. Prior research has attempted to assess the capability of LLMs to automate digital hardware design by producing superior-quality Register Transfer Logic (RTL) descriptions, particularly in Verilog. However, these tests have revealed that Verilog code production using LLMs at current state-of-the-art lack sufficient functional correctness to be practically viable, compared to automatic generation of programs in general-purpose programming languages such as C, C++, Python, etc. With this as the key insight, in this work we assess the performance of a two-stage software pipeline for automated Verilog RTL generation for combinational circuits: LLM based automatic generation of annotated C++ code suitable for high-level synthesis (HLS), followed by HLS to generate Verilog RTL. We have benchmarked the performance of our proposed scheme using the open-source VerilogEval dataset, for four different industry-scale LLMs, and the Vitis HLS tool. Our experimental results demonstrate that our two-step technique substantially outperforms previous proposed techniques of direct Verilog RTL generation by LLMs in terms of average functional correctness rates, reaching a score of 0.86 in pass@1 metric.
In recent years, significant effort has been put into developing formal verification approaches by both academic and industrial research. In practice, these techniques often give satisfying results for some types of circuits, while they fail for others. A major challenge in this domain is that the verification techniques suffer from unpredictability in their performance. The only way to overcome this challenge is the calculation of bounds for the space and time complexities. If a verification method has polynomial space and time complexities, scalability can be guaranteed. In this monograph, we propose Polynomial Formal Verification (PFV) of arithmetic circuits. We discuss the importance and advantages of PFV. Subsequently, we prove that PFV of different types of arithmetic circuits, including adders, multipliers, and Arithmetic Logic Units (ALUs) is possible. Furthermore, we calculate the exact upper-bound space and time complexities of verifying these circuits.
The recent development of cloud computing and edge computingshows great promise for the Connected and AutomatedVehicle (CAV), by enabling CAVs to offload theirmassive on-board data and heavy computing tasks. Leveragingthe Internet of Things (IoT) technology, different entitiesin the intelligent transportation system (e.g., vehicles, infrastructure,traffic management centers, etc.) get connectedwith each other, thus making the entire system smarter,faster, and more efficient. However, these advances alsobring significant challenges to public authorities, industry,as well as scientific communities. In terms of system designand control, current cloud and edge architecture of CAVsneed to be refined or even redesigned to better function underuncertainties in demand, and to better cooperate withexisting conventional vehicles and infrastructure. From theperformance assessment perspective, models and simulationtools based on artificial intelligence and big data have beenwidely developed for validation and evaluation of cloud computingand edge computing, but the validity of these modelsneeds to be re-examined with field implementations. Finally, while the increasing connectivity among vehiclesand infrastructures may help improve their perception of theenvironment and enable coordinated decision making, it alsopresents new challenges to ensure system safety and security,with inherent disturbances to wireless communication networksand also the inevitably larger attack surface that maybe exploited by malicious attacks. In this tutorial, expertsfrom academia and industry will introduce the trends andchallenges of applying cloud and edge computing for CAVs,highlight representative works in the literature and discusstheir limitations, present new promising solutions, and outlinefuture directions in research and engineering. Particularfocus will be given to methodologies and tools for buildingdigital twin frameworks with cloud and edge computing forCAVs, quantitative and formal analysis for ensuring CAVsafety under disturbances and uncertainties, system-levelCAV security threat landscape and defense solution space,and experiences from practical deployment of cloud andedge computing for CAVs.
