Collective operations that involve multiple or all processes/threads within a parallel program are critical in multicore chips and parallel systems, particularly for data-intensive applications. However, many existing electrical network systems struggle to efficiently support these operations, leading to significant overhead and reduced performance. Optical solutions have been proposed to address the challenges due to their high-speed transmission and low-power consumption. Moreover, the synergy between photonic technologies and Residue Number System offers an efficient alternative for computing because of their high parallelism and the opportunity for compute-in-network capabilities.Here, we propose PRACO, a Photonic Residue-Number Architecture for Collective Operations. It establishes a photonic network at the chip level to accelerate communication, computation, and synchronization among multi-cores in the system. Moreover, its compute-in-network capability allows for performing computations during data transmission, which minimizes data movement and further reduces latency and power consumption. Furthermore, the network enables high-speed synchronization barriers, which allows faster coordination between cores, improving overall system efficiency. Compared to an electrical network, our simulation results show that PRACO achieves up to an order of magnitude speedup for collective operations, along with a significant decrease in energy consumption.
Movement control in autonomous robots requires low-power, real-time models, especially for bio-mimetic locomotion in challenging terrains. Human intervention is often impractical in such environments, making specialized neural networks like central pattern geterators critical for offloading computational resources. This paper presents a controller for a bipedal robot using a modified spiking neuron model, adapted for efficient deployment on field-programmable gate arrays. Key modifications were made to ensure lightweight, real-time performance. Additionally, we leverage a unique open-source neuromorphic software platform for the network design and deployment, making the technology accessible to developers aiming to implement autonomous robot locomotion.
Scientific computing, data analytics and artificial intelligence (in particular with the proliferation of large language models) are driving an explosive growth in computing needs. However, leading-edge high-performance computing systems composed of digital CMOS-based processing elements are reaching physical limits that do not allow any more significant gains in energy efficiency. As we progress towards post-exascale computing systems disruptive approaches to break this barrier in energy efficiency are required. Novel analog and hybrid digital-analog systems promise improvements in energy efficiency of orders of magnitude. Among the various solutions under exploration, biochemical computing has the potential to enable a new type of computing devices with immense computational power. These device can harness the efficiency of biological cells in solving optimization problems (chemical reactions naturally converge to optimal steady states) and are scalable by considering increasingly larger reaction systems or vessels, potentially meeting the high-performance requirements of scientific computing. However, several theoretical and practical limitations still exists going from how we formulate and map problems to chemical reaction networks (CRNs) to how we should implement actual chemical reaction computing devices. In this paper, we propose a framework for chemical computation using biochemical systems and present initial components of our approach: an abstract chemical reaction dialect, implemented as a multi-level intermediate representation (MLIR) compiler extension, and a path for representing mathematical problems with CRNs. We demonstrate the potential of this approach by emulating a simplified chemical reservoir device. This work lays the foundation for leveraging chemistry’s computing power to create energy-efficient, high-performance computing systems for contemporary computing needs.
Neuromorphic computing is a promising avenue to improve processors past the limits imposed by the decline of Moore’s Law and Dennard Scaling. However, some neuromorphic computing workflows are heavily bottlenecked by passing data in-between a neuromorphic processor and a CPU because intermediate values need to be processed with arithmetic and Boolean operations. An active research field seeks to eliminate this bottleneck by executing arithmetic and Boolean operations on neuromorphic processors. Specifically, researchers encode numbers in spikes, then use hand-crafted spiking neural networks (SNNs) to perform the necessary operations on the encoded numbers. The performance of an encoding is often evaluated using addition as a proxy for the other arithmetic and boolean operations. However, how to effectively utilize graded spikes, which enable neurons to send and receive an integer value with each spike, is still an open question. Answering this question is challenging because we lack neuron models that support graded spikes. We propose the Overflow neuron model, which does support graded spikes, to mitigate this challenge. We then use the Overflow neuron to create three novel unsigned integer encodings and adder SNNs that take advantage of graded spikes. We compare how our graded spike-based encodings scale against existing encodings, demonstrating that using graded spikes can decrease the number of neurons, synapses, and spikes in SNNs. Finally, we estimate the hardware costs of using graded spikes and show that the reduction in neurons, synapses, and spikes from using graded spike-based encodings translates into a reduction in power consumption and latency. In summary, we utilize graded spikes to perform addition on neuromorphic processors and show that our graded spike-based methods outperform non-graded spike-based methods.
Superconducting logic offers the potential for incredibly high speed, low power computation, due to its gate level clocking and a lack of resistive losses. This results in large, statically scheduled pipelines with clock speeds up to 50 GHz, offering orders of magnitude better throughput than modern digital systems. To fully utilize these pipelines data must be very carefully orchestrated both outside of the system and within the pipeline itself. However, memory systems, data dependent operations, and IO introduce timing uncertainty which can cause a significant degradation in throughput and utilization. In the digital domain a rich set of latency insensitive design (LID) principles exist for this problem, but the tight combinational feedback inherent to their operation introduces a new set of challenges when integrated with single flux quanta (SFQ) based designs.We investigate these challenges by examining two classical methods for LID, the ready/valid protocol and LID-1ss. We show how a naive, direct implementation of these protocols removes much of the benefits of superconducting logic. We then explore how LID-1ss can be optimized for SFQ, resulting in better throughput and a simpler design. However, this optimized version still significantly reduces the maximum potential throughput, motivating us to propose Superconnectors: a novel SFQ-specific architecture for LID. Superconnectors leverage passive transmission line buffers, asynchronous race logic control signals, and batched transactions for a hardware design that has minimal impact on the underlying logic and throughput. We then demonstrate Superconnectors with a merge operation on an array of multipliers, introducing 44% less pipeline stall than the optimized LID-1ss approach with no impact to the achievable clock speed of the underlying module.
Noisy qubit devices limit the fidelity of programs executed on near-term or Noisy Intermediate Scale Quantum (NISQ) systems. The fidelity of NISQ applications can be improved by using various optimizations during program compilation (or transpilation). These optimizations or passes are designed to minimize circuit depth (or program duration), steer more computations on devices with lowest error rates, and reduce the communication overheads involved in performing two-qubit operations between non-adjacent qubits. Additionally, standalone optimizations have been proposed to reduce the impact of crosstalk, measurement, idling, and correlated errors. However, our experiments using real IBM quantum hardware show that using all optimizations simultaneously often leads to sub-optimal performance and the highest improvement in application fidelity is obtained when only a subset of passes are used. Unfortunately, identifying the optimal pass combination is non-trivial as it depends on the application and device specific properties.In this paper, we propose COMPASS, an automated software framework for optimal Compiler Pass Selection for quantum programs. COMPASS uses dummy circuits that resemble a given program but is composed of only Clifford gates and thus, can be efficiently simulated classically to obtain its correct output. The optimal pass set for the dummy circuit is identified by evaluating the efficacy of different pass combinations and this set is then used to compile the given program. Our experiments using real IBMQ machines show that COMPASS improves the application fidelity by 4.3x on average and by up-to 248.8x compared to the baseline. However, the complexity of this search scales exponential in the number of compiler steps. To overcome this drawback, we propose Efficient COMPASS (E-COMPASS) that leverages a divide-and-conquer approach to split the passes into sub-groups and exhaustively searching within each sub-group. Our evaluations show that E-COMPASS improves fidelity by 3.0x on average and by up-to 257.1x compared to the baseline while reducing COMPASS overheads by 200x and up to 327x.
Using an ensemble of neural networks is an effective means of quantifying the uncertainty of an output prediction. However, the memory cost of storing a large ensemble of neural networks quickly becomes prohibitive and limits their applicability. This paper details a three-stage in-memory computing circuit that performs analog-domain vector-matrix multiplication between an input voltage vector and a rank-1 compressed weight ensemble stored in the conductances of three Memristor arrays. For wide layers (thousands of neurons) and large ensemble sizes (hundreds to thousands of models), this circuit reduces the required number of Memristors by between two and three orders of magnitude relative to a non-compressed ensemble. Similarly, compared to a single neural network, the increase in the number of Memristors may be less than two-fold. We report SPICE simulations of the circuit and observe that 75% of total error does not deviate by more than 25% of the ideal value. A statistical analysis of the circuit explains these observations and offers insights regarding how the circuit may be improved.
Due to the limitations of current NISQ systems, error mitigation strategies are under development to alleviate the negative effects of error-inducing noise on quantum applications. This work proposes the use of machine learning (ML) as an error mitigation strategy, using ML to identify the accurate solutions to a quantum application in the presence of noise. Methods of encoding the probabilistic solution space of a basis-encoded quantum algorithm are researched to identify the characteristics which represent good ML training inputs. A multilayer perceptron artificial neural network (MLP ANN) was trained on the results of 8-state and 16-state basis-encoded quantum applications both in the presence of noise and in noise-free simulation. It is demonstrated using simulated quantum hardware and probabilistic noise models that a sufficiently trained model may identify accurate solutions to a quantum applications with over 90% precision and 80% recall on select data. The model makes confident predictions even with enough noise that the solutions cannot be determined by direct observation, and when it cannot, it can identify the inconclusive experiments as candidates for other error mitigation techniques.
The key limitation of physics-inspired hardware accelerators such as Ising machines (IM) or Hopfield neural networks (HNN) is their lack of support of higher order couplings of spins/neurons. As a result, many classes of combinatorial optimization problems featuring polynomial interactions (PUBO) require quadratic hardware embeddings, QUBO mappings. Such embeddings were shown to risk severe performance reduction due to mismatched configuration space features (energy landscape) compared to the native space formulation. Here, we propose a gradient matching (GM) algorithm which leverages existing IM or in-memory HNN architectures and approximately recovers the native energy landscape. We show an exponential scaling advantage of the GM algorithm time-to-solution. Finally, we propose a hardware design to physically realize our GM in an HNN-based solver.
The pursuit of high-performance and energy-efficient computing for data-intensive algorithms such as deep neural networks (DNN) opens up exciting opportunities for emerging non-volatile memories (NVM). Particularly, implementing such non-volatile memory units in crossbar arrays as weight matrix storage can provide highly parallel and efficient means of processing matrix-vector multiplications, providing synaptic functionality for the neuromorphic computing paradigm. While numerous memristive and phase-change device systems have been investigated for synaptic crossbar arrays, it remains challenging to provide robust and efficient device technology for multi-bit (analog) synapses. In this work, a multi-level spintronic device based on a magnetic tunnel junction (MTJ) device is proposed and studied. By integrating a standard MTJ free layer exchange coupled with a granular magnetic nanostructure, multiple near-continuous resistive states can be induced thanks to the distribution of the energy barrier among individual magnetic grains. Our simulation analysis demonstrated superior scalability with small variability compared to other means of multi-level devices. System-level simulation demonstrates that enabling 2bit per cell MRAM crossbars leads up to 3.2x improvement in hardware efficiency while maintaining the inference accuracy.
In-memory computing is a promising solution for solving the von-Neumann bottleneck. In particular, computational random-access memory (CRAM) is a promising form of in-memory computing where cascading logic operations can be performed directly within the memory array. However, a recent experiment utilizing magnetoresistve devices as the memory element in CRAM only gave the correct answer in 63 % of trials. One way to improve the accuracy is to build CRAM cells using resistive devices with larger ON/OFF ratios. In this study, we explore the performance of CRAM using resistive random-access memory (ReRAM) cells. Using experimental data obtained from various TiN/TiOX-based ReRAM devices in Monte Carlo simulations, we determine that the performance of the full adder operation using ReRAM based CRAM is still subject to the same inaccuracies as CRAM that utilizes magnetoresistive devices. However, our analysis reveals that by reducing the write voltages and removing the effects of complementary resistive switching in the ReRAM devices, 100 % accuracy over 100,000 trials can be achieved.
Analog circuits can be used to efficiently implement Ising machines, a class of recurrent neural networks that gives good solutions to NP-hard problems. However, designers are faced with numerous choices when deciding how to implement the activation function, weighted connections, and network architecture of an analog Ising machine. This paper explores the tradeoffs between different Ising machine architectural choices (the activation function, weighted connections, and network architecture) and discusses the best combination of choices to solve different NP-hard problems.
In this work, we present HiAER-Spike, a modular, reconfigurable, event-driven neuromorphic computing platform designed to execute large spiking neural networks with up to 160 million neurons and 40 billion synapses - roughly twice the neurons of a mouse brain at faster-than real-time. This system, which is currently under construction at the UC San Diego Supercomputing Center, comprises a co-designed hard-and software stack that is optimized for run-time massively parallel processing and hierarchical address-event routing (HiAER) of spikes while promoting memory-efficient network storage and execution. Our architecture efficiently handles both sparse connectivity and sparse activity for robust and low-latency event-driven inference for both edge and cloud computing. A Python programming interface to HiAER-Spike, agnostic to hardware-level detail, shields the user from complexity in the configuration and execution of general spiking neural networks with virtually no constraints in topology. The system is made easily available over a web portal for use by the wider community. In the following we provide an overview of the hard- and software stack, explain the underlying design principles, demonstrate some of the system’s capabilities and solicit feedback from the broader neuromorphic community.
Novel algorithms leveraging neuromorphic computation are on the forefront of algorithm design. Here, we investigate how stochastic devices integrate and perform with a novel neuromorphic algorithm for solving MAXCUT problems in graphs. We evaluate how using magnetic tunneling junctions (MTJs) as the device to generate random numbers impacts the neuromorphic MAXCUT algorithm. We use both experimental MTJ data, as well as a model of the device behavior to investigate MTJ performance on this task. We also leverage the use of evolutionary optimization to tune the MTJ device to maximize performance on the algorithm and minimize energy usage of the device.
Neuromorphic computing offers exciting possibilities for embedded systems and edge-computing, due to its combination of computational ability and low size, weight, and power. However, open source solutions for embedded neuromorphic computing are lacking. In this paper, we present open source support for the RISP neuroprocessor, which features simple integrate-and-fire neurons and synapses with discrete delays. There are two software repositories to support RISP - one that provides simulation and network manipulation, and one that implements RISP networks on FPGAs. We detail each of these, discuss capacity and performance, and present examples. Highlights include the large networks supported by commodity FPGAs, with tens of thousands of neurons and synapses. The UART communication is a clear bottleneck; however there are multiple straightforward avenues for improving communication.
Innovative accelerator architectures aim to play a critical role in future performance improvements under ceilings imposed by the end of Moore’s Law. Analog mesh computers are a class of such accelerators, designed to minimize time-to-solution by solving partial differential equations in one shot. However, the limited programmability of analog mesh computers does not support the PDE-solver requirement to match arbitrary PDE mesh shapes. In this work, we introduce a chiplet-based architecture capable of solving arbitrary PDE mesh shapes by chaining neural network acceleration chiplets and analog mesh computers. Specifically, we use physics-informed neural networks to infer the values at the perimeter of the analog mesh computer, and then use the analog mesh computer to solve for the remainder of the PDE. We then investigate resource scheduling strategies for the chiplet-based PDE acceleration architecture. Additionally, we propose a figure of merit that enables comparisons between classes of PDE accelerators. We show that the chiplet-based accelerator shows a speedup of 2x when compared to existing solutions.
Hafnia-based ferroelectric devices are promising for future embedded electronics, but their performance is largely untested when integrated into neurormorphic computing architectures. In this work, we investigate how these devices perform in a variety of classification and control tasks. Within our framework, we show that different read voltages on these devices can have an impact on performance, but overall, these devices as synapses can achieve comparable or better performance within a neuromorphic system than neuromorphic systems with more continuous, higher precision synaptic weights.
The increasing difficulty in continued development of digital electronic logic has led to a renewed interest in alternative approaches. Oscillatory computing is one such approach that leverages alternative physical systems and computation strategies, but it lacks high-level paradigms for system design and programming. We address this gap by describing a model based on hyperdimensional computing that serves as an "instruction set" to integrate oscillatory networks into algorithms for real-valued computing. The expressiveness and compositionality of these instructions allow oscillatory systems to implement both common tasks and novel functions, providing a clear computational role for many emerging hardware devices. We detail the computational primitives of this system, prove how they can be executed via oscillatory systems, quantify the performance of these operations, and apply them to execute multiple tasks including compression, factorization, and classification.
Addressing the growing demands of artificial intelligence (AI) and data analytics requires new computing approaches. In this paper, we propose a reconfigurable hardware accelerator designed specifically for AI and data-intensive applications. Our architecture features a messaging-based intelligent computing scheme that enables dynamic programming at runtime using a minimal instruction set. To assess our hardware's effectiveness, we conducted a case study using TSMC 28nm technology node. The simulation-based study benchmarks our hardware against the Tensor Processing Unit (TPU) and involves analyzing a protein network using the computationally demanding PageRank algorithm. The results indicate that our hardware can analyze a 5,000-node protein network in just 213.6 milliseconds over 100 iterations. Moreover, our design outperforms systolic array based TPU demonstrating an 11% reduction in latency for matrix vector multiplication. These outcomes signify the potential of our design to achieve cutting-edge performance in next-generation AI applications.
This paper presents an easy-to-implement approach to mitigate the challenges posed by barren plateaus (BPs) in randomly initialized parameterized quantum circuits (PQCs) within variational quantum algorithms (VQAs). Recent state-of-the-art research is flooded with a plethora of specialized strategies to overcome BPs, however, our rigorous analysis reveals that these challenging and resource heavy techniques to tackle BPs may not be required. Instead, a careful selection of distribution range to initialize the parameters of PQCs can effectively address this issue without complex modifications. We systematically investigate how different ranges of randomly generated parameters influence the occurrence of BPs in VQAs, providing a straightforward yet effective strategy to significantly mitigate BPs and eventually improve the efficiency and feasibility of VQAs. This method simplifies the implementation process and considerably reduces the computational overhead associated with more complex initialization schemes. Our comprehensive empirical validation demonstrates the viability of this approach, highlighting its potential to make VQAs more accessible and practical for a broader range of quantum computing applications. Additionally, our work provides a clear path forward for quantum algorithm developers seeking to mitigate BPs and unlock the full potential of VQAs.
