In this paper, we present a new low-latency method based on Finite State Machines (FSMs) for basic arithmetic as well as trigonometric functions in single-precision IEEE-754 standard format on a Virtex-7 Field-Programmable Gate Array (FPGA). Basic floating-point arithmetic methods are optimized to reduce latency for scalar operations where the cost of pipelining cannot be amortized over longer data streams. We provide additional trigonometric functions necessary for image correlation that are not found in other open-source libraries. Our trigonometric functions are optimized for use in system-on-chip FPGA architectures where Block Random Access Memories (BRAMs) are needed for buffering data and not available to hold large lookup tables. Results are presented comparing delay, area, operating frequency, and memory utilization of our new methods to previous works presented in the literature as well as the built-in Vivado IP. Comparisons show that the proposed approach offers key improvements in delay and area for basic arithmetic operations. Specific to trigonometric functions, our implementations offer a reduction in memory requirements and a higher operating clock frequency compared to existing works.
Despite all the available commercial and open-source frameworks to ease deploying FPGAs in accelerating applications, the current schemes fail to support sharing multiple accelerators among various applications. There are three main features that an accelerator sharing scheme requires to support: exploiting dynamic parallelism of multiple accelerators, sharing accelerators among multiple applications, and providing a nonblocking congestion-free environment for multiple applications to call multiple accelerators. In this paper, we developed a scalable fully functional hardware controller, called UltraShare, with a supporting software stack that provides a dynamic accelerator sharing scheme through an accelerators grouping mechanism. UltraShare allows software applications to fully utilize FPGA accelerators in a non-blocking congestion-free environment. Our experimental results for a simple scenario of a combination of three streaming accelerators invocation show an improvement of up to 8x in throughput of the accelerators by removing accelerators idle times.
In this paper, we first propose the design of Temporal-Carry-deferring MAC (TCD-MAC) and illustrate how our proposed solution can gain significant energy and performance benefit when utilized to process a stream of input data. We then propose using the TCD-MAC to build a reconfigurable, high speed, and low power Neural Processing Engine (TCD-NPE). We, further, propose a novel scheduler that lists the sequence of needed processing events to process an MLP model in the least number of computational rounds in our proposed TCD-NPE. We illustrate that our proposed TCD-NPE significantly outperform similar neural processing solutions that use conventional MACs in terms of both energy consumption and execution time.
This paper describes the architecture of a FPGA-based high-performance training accelerator for neural networks. Our accelerator uses a hybrid embedded floating point and soft logic approach to implement truncated floating-point datapaths, including bfloat16 and bfloat14. The proposed multi-layer perceptron (MLP) training architecture is the highlight of a general methodology for developing high-performance accelerators written in OpenCL and incorporating a systolic-array GEMM engine with off-chip memory interfaces. The accelerator is capable of 5 Tflops on a mid-range FPGA device and achieves over 90% of the peak efficiency during training, thus demonstrating the versatility of using FPGAs as neural network training accelerators.
Blockchain technology has gained immense popularity in the recent years due to its decentralized computing architecture. While it originally emerged as a technology for (crypto)currencies, it has since found many different application areas including (but not limited to) payments, money transfers, smart contracts, supply-chain management, networking, IoT, etc. Initially, it was only Bitcoin, the de facto standard for cryptocurrencies, but then it was followed by several (in fact hundreds of) others. Each new cryptocurrency had or claimed to have certain advantages over Bitcoin, such as transaction speed and cost. However, they all relied on the original idea of distributed ledger where each block has maintained a complete history of each transaction in the network. Blockchain technology has more recently been challenged by two new technologies called Tangle and Hashgraph, which are “directed acyclic graphs”, i.e. in layman's terms blockchains without blocks and chains. IOTA network is the original Tangle technology, which relies on ternary arithmetic architecture and uses ternary hash function “Troika”. It works on GF(3) and its design follows the sponge construction. Two of the main claims of IOTA are scalability and micro-transitions, both of which are likely to utilize compact hardware platforms in practical implementations. In this paper, an almost-zero logic compact and yet adequately fast hardware architectures of Troika hash function targeting reconfigurable devices are presented. The proposed architectures mainly depend on the utilization of BRAMs on FPGAs. Three different RAM-based hardware implementations have been realized on Xilinx Artix-7xc7a12tcpg238-3 device; all using only a single BRAM tile with minimal number of LUTs and FFs. The proposed architectures can easily be implemented on different reconfigurable devices with similar efficiency. To the best of our knowledge, this is the first reported hardware implementation of Troika hash function on reconfigurable devices which is also compact and fast.
With the advent of advanced signal processing techniques and spin-based devices using novel Analog to Digital Converter (ADC) architectures, a novel framework for simulating spin-based ADCs is developed. This proposed simulation framework, called Spinbased ADC Interactive Simulator has been developed to provide insights on use of commercially-available 2-terminal Magnetic Tunneling Junction (MTJ) devices to implement adaptive non-uniform Compressive Sensing (CS) techniques for both technical and educational purposes. MTJ devices can facilitate adaptive CS techniques using nonuniform sampling while reduction in energy consumption of sampling operations, storage, and data transmission overheads. An interactive simulation framework is developed to allow the user to fully-manipulate simulation setup and parameters associated with the spin-based devices. This provides a mean for the users to perform various simulation runs using different parameters to observe the behavior of the Spin-based ADCs under a variety of scenarios and test cases. The simulation results include energy consumption of each spinbased device along with signal transition illustrations of each device at various sampling intervals. Moreover, links to additional educational resources are provided to further the understanding of the Spin-based ADCs being modeled. Future work includes development of educational content for engagement and attraction of high school students into STEMrelated fields and an export functionality that enables extracting the results to create spreadsheet documents. Keywords— Sampling Rate, Quantization Resolution, Compressive Sensing, Magnetic Tunnel Junction, Beyond-CMOS Devices, Analog to Digital Converter (ADC).
Although high-level synthesis (HLS) improves designer productivity through abstraction, FPGA high-level synthesis stills suffers from lengthy compilation that limits the number of design iterations a developer can achieve per day. One method of minimizing these compile times is compiling designs with innate programmability, aka FPGA overlays, and using their runtime configuration to implement functional changes, as opposed to recompiling the design. In this paper, we introduce Seiba, an application development approach that integrates HLS circuits with FPGA overlays to create reconfigurable platforms that are rapidly configured to reduce development time. As a dual-layer compilation approach, Seiba enables users to choose an appropriate tradeoff between productivity and overhead by implementing incremental changes quickly through overlay configuration or efficiently through FPGA recompilation. To handle this integration, our approach uses a novel overlay architecture that offers flexible overlay configuration which can “patch” and redirect execution from an application circuit to runtime configurable overlay functional units. Our results show that by leveraging the overlay's runtime configurability, our development flow can significantly reduce the number of FPGA compilations in a development cycle.
FPGAs are an excellent target for real-time video processing as they provide large amounts of low-level parallelism, low latency, and high bandwidth. However, creating real-time video processing systems on an FPGA is tedious and requires significant effort and low-level digital design skills. This paper presents a technique for creating complex real-time video processing pipelines relatively quickly and easily using partial reconfiguration (PR). A static FPGA system is created that provides a template for a variety of partially reconfigurable video processing cores. A library of video filters has been created that can be inserted into the template regions. At run-time, the user can select the topology of video cores and customize these cores to create complex and unique video pipelines without any understanding of low-level FPGA details. This paper demonstrates this technique with a library of 11 partial reconfigurable regions and 16 video processing cores operating on the Xilinx PYNQ system.
Recently, significant attention has been given to hardware realization of Orthogonal Matching Pursuit (OMP) algorithms for signal reconstruction. Some CMOS-only approaches have been proposed in the literature which minimize overheads impacting throughput by exploiting parallelism within OMP techniques. Herein, an approach using hybrid spin-CMOS hardware is presented as a reconfigurable logic fabric utilizing a palette of spintronic and MOS components. The resulting fabric utilizes slice-organized analog blocks providing amplifiers, transistors, capacitors, and low-/high-barrier Magnetic Tunnel Junctions (MTJs) which are configurable to realize OMP's required squaring and square-root operations in analog. Digital functional blocks include 6-input fracturable look up tables, and a spin-based analog-to-digital converter to realize matrix inversion needed by OMP. These functional blocks are connectable via programmable interconnect to a non-volatile crossbar to perform low energy vector-matrix multiplication with reduced area. Simulation results indicate a 5-fold reduction in energy consumption and a 26-fold decrease in area requirement compared to CMOS-only approaches.
Many numerical simulation applications from the scientific, financial and machine-learning domains require large amounts of compute capacity. They can often be implemented with a streaming data-flow architecture. Field Programmable Gate Arrays (FPGA) are particularly power-efficient hardware architectures suitable for streaming data-flow applications. Although numerous programming languages and frameworks target FPGAs, expert knowledge is still required to optimise the throughput of such applications for each target FPGA device. The process of selecting which optimising transformations to apply, and where to apply them is dubbed Design Space Exploration (DSE). We contribute an elegant and efficient compiler based DSE strategy for FPGAs by merging information sourced from the compiled application's semantic structure, an accurate cost-performance model and a description of hardware resource limits for particular FPGAs. Our work leverages developments in functional programming and dependent type theory to bring performance portability to the realm of High-Level Synthesis (HLS) tools targeting FPGAs. We showcase our approach by presenting achievable speedups for three example applications. Results indicate considerable improvements in throughput of up to 58× in one example. These results are obtained by traversing a minute fraction of the total Design Space.
The processing demands of current and emerging applications, such as image/video processing, are increasing due to the deluge of data, generated by mobile and edge devices. This raises challenges for a vast range of computing systems, starting from smart-phones and reaching cloud and data centers. Heterogeneous computing demonstrates its ability as an efficient computing model due to its capability to adapt to various workload requirements. Field programmable gate arrays (FPGAs) provide power and performance benefits and have been used in many application domains from embedded systems to the cloud. In this paper, we used a closely coupled CPU-FPGA heterogeneous system to accelerate a sliding window based image processing algorithm, Canny edge detector. We accelerated Canny using two different implementations: Code partitioned and data partitioned. In the data partitioned implementation, we proposed a weighted round robin based algorithm that partitions input images and distributes the load between the CPU and the FPGA based on latency. The paper also compares the performance of the proposed accelerators with separate CPU and FPGA implementations. Using our hybrid CPU-FPGA based algorithm, we achieved a speedup up to 4.8× over a CPU-only and up to 2.1× over a FPGA-only implementations. Moreover, the estimated total energy consumption of our algorithm is more efficient than a CPU-only implementation. Our results show a significant reduction in energy delay product (EDP) compared to the CPU-only implementation, and comparable EDP results to the FPGA-only implementation.
Homomorphic Encryption (HE) allows for encrypted data to be sent to, stored, and operated on by untrusted parties without the risk of privacy compromise. The benefits and applications of HE are far reaching, especially in regard to cloud computing. However, current HE solutions require a large number of resource intensive arithmetic operations such as high precision, high degree polynomial multiplication. This work aims to accelerate the multi-precision arithmetic operations used in HE with specific focus on an implementation of the Schönhage-Strassen Fast Fourier Transform (FFT)-based multiplication algorithm. It is planned to be incorporated into a larger HE library of arithmetic functions tuned for High-Level Synthesis (HLS) that enables flexible solutions for hardware/software systems on reconfigurable cloud resources. The developed FFT based polynomial multiplier exhibits flexibility in the selection of HE security parameters facilitating its use in a wide range of schemes and applications. The design yields substantial speedup over the polynomial multiplication functions implemented in the Number Theory Library (NTL) utilized by software based HE solutions.
This paper presents the TURTLE fault injection platform for inserting faults into SRAM FPGAs. The TURTLE system is designed to gather significant fault injection data to test and validate radiation-induced single-event upset (SEU) mitigation techniques for FPGAs. The TURTLE is a low-cost fault injection platform that emulates upsets within the configuration memory (CRAM) of an FPGA through partial reconfiguration. This work successfully implemented the proposed architecture and performed several successful fault injection campaigns on multiple designs and SEU mitigation techniques. Results in this paper show large amounts of data collected from a fault injection campaign used to validate the PCMF SEU mitigation technique. Over 170 million injections were performed using the TURTLE for this campaign.
High-Level Synthesis (HLS) allows not only for quicker prototyping, but also faster and more widespread design space exploration. In this work we designed a turbo decoder using Vivado HLS, which has not previously been explored. Our turbo decoder was designed to allow for easy design space exploration, both of algorithmic turbo decoder parameters as well as HLS parameters. Data and analysis on the design space is presented for approximately 200,000 variations with an emphasis on the needed trade-offs when designing a turbo decoder.
In this paper we propose a technique to minimise the area overhead of a double buffered implementation of Radix-4 Fast Fourier Transformation (FFT). Our proposal circumvents the need for double buffering by exploiting opportunities in the specific data reordering of the buffers that are needed when implementing a fully pipelined FFT. By using the same read and write pattern, a single buffer is sufficient to perform data reordering while maintaining data integrity without degrading performance. We demonstrate this approach in an FPGA implementation. As a result of our optimisation, the memory depth can be reduced by a factor of two with very small overhead in control logic complexity.
Modulo scheduling is a powerful method to increase throughput in high-level synthesis for digital hardware design. When facing large designs, optimal approaches are likely to time out and heuristics fail to provide satisfying throughput and latency. We propose an isomorphic subgraph-based reduction of the input data-flow graph (DFG) that is applied before scheduling, in order to solve the modulo scheduling problem faster without changing the optimal initiation interval (II) and allocated hardware. Our results show a solving time speedup of 5× on average and up to 102× for large designs. Using the proposed pre-processing step, the II achieved could be reduced by 33% on average for SDC-based modulo schedulers. And in ILP-based scheduling, we could classify 15% more solutions as optimal within the same time compared to solutions provided without applying our transformation.
Robotic applications are becoming more complex every day because they rely on multiple heterogeneous sensors and actuators, increasing the computational demand. Energy efficiency becomes an important factor to consider as battery powered robots have limited energy budget. Algorithms have to be carefully implemented to achieve the expected performance. Consequently, there is a need to increase performances of embedded devices for robotics in terms of computational power and energy efficiency. This work presents a methodology to design an architecture for custom embedded hardware applications implemented in Field Programmable Gate Arrays to be compatible with the mainstream Robot Operating System (ROS). Therefore, highly computational algorithms can be implemented as a dedicated hardware module to increase the processing power of any heterogeneous robotic system. A modular design is foreseen to ease the adaptability to changes in the system. A generic interface for all modules is chosen leading to fully customizable messages to exchange data internally or with other parts of the distributed systems.
As computation migrates to the edge, energy efficiency is becoming even more critical in the design of electronic devices. Therefore, new applications for the Internet of Things pose a challenge for designers to find the optimal balance between performance and energy consumption. While Coarse Grained Reconfigurable Architectures (CGRA) have been an alternative to provide the required acceleration, they are far from being the most energy-efficient, since their functional units may be underutilized by some applications. In this work, we introduce a novel approach to handle these CGRA resources, which leverages the variable usage of functional units due to the application program phases. By using our new approach and performing power-gating of under-utilized parts of the CGRA, we demonstrate that it is possible to achieve reductions of up to 52.3% in power dissipation and 75% in energy consumption.
High-Level Synthesis (HLS) is a process that translates traditional software languages (C/C++/Java) into either a hardware description language representation or a netlist representation that, ultimately, can be implemented on an FPGA device, for example. The original goal was to make advanced computing accelerators accessible to embedded computing systems programmers. However, the technology has attracted the interest of high-performance computing (HPC) programmers as well. This would be a huge benefit because labor statistics suggest that every year 10x as many software programmers graduate for every hardware designer [1]. However, HPC programmers use large in-core datasets versus the transient, streaming data sets that are common in embedded systems. Looking forward, it is appropriate to explore the behavior of HLS with next-generation memory technologies, like the Hybrid Memory Cube (HMC).
Applying FPGAs and real-time bare-metal code in experimental robots has many benefits but puts high demands on the skills of students and researchers. This contribution presents an interface between FPGA, hard-macro microcontroller cores and the popular middleware ROS implemented on a single chip.
