ABSTRACT Multilevel inverters (MLIs) are critical for enhancing power quality in medium‐voltage applications, yet traditional topologies often suffer from low reliability and high costs due to the excessive number of power semiconductor switches required to achieve high‐resolution outputs. This paper proposes a novel single‐phase asymmetrical MLI topology capable of synthesizing a 29‐level output voltage waveform with a significantly minimized component count. The proposed configuration utilizes four DC voltage sources and 15 unidirectional power switches to achieve 29‐level output voltage waveform, representing a substantial reduction in active components compared with the conventional cascaded H‐bridge (CHB) inverter which requires 56 switches for equivalent performance. A distinct advantage of this topology is its simplified control architecture; by employing combinational logic to derive complementary switching states, the system requires only eight independent gate driver signals,and other seven is to be logically derived from the eight independent signals, thereby reducing the computational burden on the digital controller. The circuit operation is regulated using the phase disposition pulse width modulation (PD‐PWM) technique to ensure a near‐sinusoidal output with low total harmonic distortion (THD). The theoretical framework is validated through extensive simulations in PSIM and MATLAB/Simulink, and is corroborated by experimental results from a laboratory prototype. Comparative analysis demonstrates that the proposed structure offers a compact, cost‐effective solution with reduced switching losses and installation space requirements suitable for renewable energy integration.
ABSTRACT This paper proposes a sensorless control strategy for a single‐phase asymmetric T‐type power factor correction (PFC) converter. Unlike traditional multi‐loop control methods, which require measurement of input AC voltage, output DC voltage, and inductor current, the proposed control algorithm relies solely on feedback signals from the input and output voltages. This method effectively regulates the output voltage and achieves power factor correction of the input current while eliminating the impact of inductor current sampling errors on system performance, reducing the number of sensors, and simplifying controller design. The control strategy utilizes hybrid unipolar and bipolar pulse width modulation (PWM) techniques to accommodate varying input AC voltage requirements. Simulation results show that the proposed control strategy successfully achieves power factor correction and output voltage adjustment while reducing the total harmonic distortion (THD) of the current in the circuit.
ABSTRACT The paper presents an improved quadratic boost converter with an integrated switched‐capacitor charge pump capable of achieving high voltage gain at a lower duty cycle. The advantage of the proposed converter is its use of a single switch, which enables simple control without compromising the common ground feature. The converter also features lower input current ripple, which is an important requirement. The detailed mathematical steady‐state analysis of the converter is first carried out in the continuous conduction mode of operation, along with the design of the circuit parameters. The converter is further compared with similar, recently reported quadratic boost converter topologies based on component count, switch voltage stress, current ripple, and other metrics. The small‐signal model of the converter is also formulated for stability analysis and to design a suitable control technique for closed‐loop operation. To verify the converter's performance indices, a 100 W laboratory prototype is developed, and the results are experimentally verified. The lower input current ripple, the ability to achieve a higher output voltage at a lower duty ratio, and lower switching stress make it suitable for use in a fuel‐cell‐powered electric vehicle.
ABSTRACT For wireless power transfer (WPT) systems operating in the multi‐MHz range, this paper proposes a three‐level Class converter featuring a coupled T‐type network, alongside a comprehensive parameter design methodology. This proposed method jointly ensures load‐independent low voltage stress, full‐range zero‐voltage switching (ZVS), and a stable constant‐voltage mode (CVM). First, time‐domain modeling is conducted to comprehensively analyze the constraint conditions for load‐independent operation of the topology. Second, the DC‐feed inductor of the proposed topology is innovatively integrated with planar magnetic coupled windings, reducing the inductor current ripple by up to 50%. For practical WPT applications, the coupled inductors of the T‐type network can be integrated into the transmitter coil using a bipolar winding structure to realize effective electromagnetic decoupling. To validate the theoretical analysis, a 3 MHz WPT system prototype based on LCC/S compensation was constructed. Experimental results demonstrate that the proposed circuit topology maintains ZVS and CVM operation across the full power range, with switch voltage stress consistently kept at 1.05 V DC and output voltage fluctuation within 5.2%. The proposed inverter achieves a peak efficiency of 96.3%.
ABSTRACT A compact rectenna operating at 900 MHz for wireless powered implantable devices is presented. With the bending technique of the antenna arms, the proposed rectenna volume was effectively miniaturized to only 3.13 mm 3 , establishing the smallest reported structure to date compared with literature at a similar band frequency. A monolithic integration scheme was employed, yielding a compact footprint of 250 μm × 850 μm. To achieve accurate impedance optimisation for maximum power transfer, the electrical characteristics of the incorporated elements were comprehensively characterized over a wide range of operating frequencies and input power levels. The proposed design methodology demonstrates a matching‐less rectenna integration circuitry, which aided in further reduction in the ultimate volume. Four samples have been explored, and 2 × 15 mm 2 design shows a superior low power reflection of 0.1%, which resulted in a high output voltage and power conversion efficiency of 0.84% and 7.92% at a load resistance of 14 kΩ, respectively. The maximum experimental power transmitted efficiency (PTE) of 0.0013% was obtained for the 5‐mm 2 design, corresponding to a 0.2‐V output voltage at 20‐dBm transmitted power. With a 2 × 15 mm 2 design, the rectenna delivers high PTE of 0.0504%, demonstrating competitive performance together with a significant reduction in the implementation complexity for self‐powered implanted devices.
