ABSTRACT Despite their structural simplicity, quasi‐resonant (QR) flyback converters suffer from performance degradation due to intricate parasitic elements. Conventional ideal‐mode analysis fails to capture these underlying mechanisms. To address this, this paper employs a mesh combination method to systematically identify sneak circuit modes excited by critical parasitic parameters (, , , and ). State equations and analytical voltage expressions are established for key MOSFET switching transitions (Mode2 and Mode5). Rather than merely extracting or eliminating parasitic values, the core objective of this work is to elucidate their dynamic impacts and leverage them for converter optimization. MATLAB‐based parameter scanning and experimental validations reveal that an increased secondary diode capacitance effectively suppresses turn‐off voltage spikes but simultaneously prolongs the turn‐on resonant valley time alongside the MOSFET capacitance , whereas the equivalent resistance shows negligible impact. Based on these dynamic characteristics, explicit parameter trade‐off guidelines for are proposed to optimally balance converter efficiency and device reliability.
ABSTRACT Benefiting from full load range zero‐voltage switching (ZVS), open‐loop LLC converters operating near the resonant frequency have been widely adopted in isolated dc transformer (DCX) applications. In conventional ZVS criteria, the magnetizing inductor during the dead time is typically approximated as a constant current source to drive the commutation of the bridge‐arm midpoint voltages on both sides. However, the high‐frequency resonant interaction between the semiconductor output capacitances and the resonant network during the dead time can distort the voltage and current waveforms, potentially leading to inaccurate ZVS boundary prediction and even ZVS failure. To address this issue, the commutation process involving the output capacitances and the associated resonant mechanism during the dead time are investigated in detail for a full‐bridge DCX‐LLC converter, based on which a refined magnetizing inductance boundary is derived. The proposed boundary explicitly reveals the effects of load conditions and resonant parameters on ZVS, thus providing a clearer theoretical basis for DCX‐LLC parameter design. Furthermore, a systematic design procedure is established and validated using a 160‐W, 95‐kHz prototype.
ABSTRACT Aiming at the chattering problems of the inverter system, a novel ideal sliding mode control (SMC) strategy with disturbance observer is proposed in this paper. First, the mathematical model of the T‐type three‐level inverter is presented by Delta operator discretization. Then, the SMC synthesis problems for the inverter system are addressed, such as the switching plane selected, Delta operator ideal reaching law constructed, and Delta operator SMC law designed. Next, a disturbance observer is designed to observe the disturbance and compensate the system uncertainties through its observations. Finally, simulation and experiment results show that the T‐type three‐level inverter by the proposed controller can reach the switching plane in finite time and attenuate the chattering compared with other SMC strategies. In a word, this paper addresses a class of ideal SMC strategy for inverter system and presents an outlook on its bright further developments.
ABSTRACT With an increasing number of electric vehicles (EVs) manufacturers deploying wireless power transfer (WPT) technology, the efficiency and adaptability of such systems have garnered growing attention. To address the challenge of maintaining high efficiency over a wide battery voltage range (100–420 V) in EV wireless charging systems, this paper proposes a magnetically coupled resonant WPT system based on topology reconfiguration. The transmitter employs two identically sized unipolar coils arranged with partial overlap to achieve magnetic decoupling. By controlling the switching network at the transmitter side to switch operating modes, the proposed topology achieves high‐efficiency output across four discrete voltage modes—100, 200, 300, and 400 V—without relying on a post‐stage DC–DC converter or extreme parameter regulation. Furthermore, zero‐voltage switching (ZVS) is achieved in all four modes. A unified mathematical model of the system is established to reveal its operating mechanism, and its performance is validated using a 4.1‐kW experimental platform. Experimental results demonstrate that under perfectly aligned conditions, the system efficiencies at the respective target output voltages are 90.726%, 94.908%, 95.193%, and 95.638%. Additionally, the system was rigorously tested and verified through misalignment and variable‐load experiments. The results indicate that the system can maintain high‐efficiency operation across the entire voltage range and it achieves strong anti‐misalignment robustness and favorable constant‐voltage output performance. This verifies that the proposed topology is a highly effective approach for achieving efficient and stable wireless charging over a wide voltage range.
ABSTRACT In critical‐conduction‐mode (CRM) boost power‐factor‐correction (PFC) converters, the negative inductor current required for valley switching (VS) or zero‐voltage switching (ZVS) reduces the net input charge, particularly near the line‐voltage zero crossings, and thereby causes crossover distortion. Existing digital variable‐on‐time (VOT) methods commonly rely on iterative computation or large lookup tables (LUTs), while their accuracy is also affected by resonant‐parameter deviations and signal‐chain delays. This paper proposes an explicit VOT control method with online effective resonant‐parameter updating. A cycle‐by‐cycle charge‐balance model is used to derive an explicit quadratic on‐time expression, eliminating online iterative solving and large multidimensional LUTs. Compared with the iterative reference solution, the maximum relative errors of the explicit expression are 0.77% at 110 Vac and 2.93% at 220 Vac under the evaluated operating conditions. The effective resonant parameter is updated from the measured zero‐current‐detection timing interval and is applied to both the on‐time and digital turn‐on‐delay calculations. The implemented control law accelerator routine requires approximately 2.3 μs. Experimental results obtained from a 160‐W prototype demonstrate reduced crossover distortion and improved input‐current quality compared with conventional constant‐on‐time control. At full load, the measured input‐current THD is 1.1% at 110 Vac and 4.2% at 220 Vac.
ABSTRACT Existing MOS‐only passive memristor emulators commonly rely on auxiliary MOSFET channels that conduct and switch between the on and off states, introducing channel‐current and switching‐dynamics constraints. This paper proposes a voltage‐controlled GHz‐level MOS‐only memristor emulator (i.e., VNGME). VNGME consists of three MOSFETs without explicit diodes, external passive elements, or power supplies, and its assistant MOSFET channels remain off, thereby avoiding auxiliary‐channel conduction and channel‐state transitions. It operates up to 10 GHz and occupies an area of 10.66 m 2 in the TSMC 65‐nm process. Under a 3‐V, 1‐GHz excitation, VNGME consumes 32.05 W excluding the main‐MOSFET channel power. Furthermore, VNGME's curve is tunable through external voltage inputs. Finally, VNGME is verified with CD4007. The voltage‐controlled oscillator circuit based on the proposed VNGME is presented, which can achieve stepless frequency modulation from 85.885 to 634.1 kHz via controlling VNGME.
ABSTRACT This brief presents a dual‐functional single‐stage receiver (DSR) circuit that simultaneously performs rectification and power regulation, then ensures a compact wireless charging system. The DSR circuit features an ultra‐simplified architecture consisting of only two MOSFETs and one filter capacitor. First, the operating stages and working principle of the DSR circuit are given. Then, the quantitative relationship between the charging current and the duty cycle of the pulse‐width modulation (PWM) signals is derived. Second, a low‐complexity control strategy is proposed, comprising a synchronous signal unit for generating two PWM signals and a closed‐loop control unit for constant‐current (CC)/constant‐voltage (CV) charging. Simulation results verify the DSR circuit's stable rectification and accurate CC/CV charging performance across a wide range of equivalent load resistances. Finally, experimental results demonstrate that the maximum system efficiency can reach 92.8% at a charging power of 360 W. Compared with commonly used secondary‐side power adjustment circuits, the DSR circuit offers outstanding structural and control simplicity for the WCS, mainly enabled by its single‐stage dual‐function architecture.
ABSTRACT This work presents two transistor‐level solutions to implement a double differential (DD) amplifier by using a current conveyor, which can be used as front‐ends in standalone active electrodes for superficial electromyography (sEMG) applications. Currently published DD amplifiers highlight the advantages of using second‐generation current conveyors to achieve simplified topologies, but they do not provide transistor level implementations. In this work, two solutions are presented and analyzed in detail.
ABSTRACT This work presents a generalized small‐signal modeling methodology for a family of DC–DC converters based on the four‐state switching cell with a wide conversion range (WCR‐4SSC) operating in continuous conduction mode (CCM). Although the proposed approach is derived from the well‐established state‐space averaging (SSA) technique, it simplifies the modeling process by representing the six operating stages as an equivalent two‐stage solution. The resulting averaged model is defined in terms of an equivalent duty cycle, whose expression depends on the converter operating region ( R 1 , R 2 , or R 3 ), which is determined by the rated duty cycle. A step‐by‐step procedure for obtaining the averaged model and its subsequent linearization is presented and applied to a DC–DC Ćuk converter based on the WCR‐4SSC, yielding several transfer functions of interest. To validate the proposed methodology, the analytical model is compared with the switched converter. The results show good agreement in both the frequency and time domains, confirming the accuracy of the proposed solution.
ABSTRACT With the progressive power‐electrification of conventional power systems, the penetration level of distributed generation (DG) systems has been steadily increasing. However, if improperly designed, DG systems may introduce power quality issues. In particular, when severe harmonic distortion is caused by nonlinear loads, the effectiveness of conventional harmonic mitigation approaches becomes limited. To address this issue, this paper investigates a harmonic suppression strategy implemented through the DG‐grid interface inverter. Specifically, a two‐step virtual impedance control method is proposed for voltage‐controlled DG systems to suppress harmonic components. This strategy can be seamlessly integrated into voltage‐controlled DG units, thereby improving the harmonic performance of the DG‐side current. Finally, the effectiveness of the proposed method is validated through MATLAB‐based simulations and hardware‐in‐the‐loop (HIL) experimental results.
ABSTRACT This paper presents a low‐power two‐step gray‐code counter based on self‐feedback for single‐slope analog‐to‐digital converter (SS‐ADC) in CMOS image sensor (CIS). The proposed counter implements digital correlated double sampling (D‐CDS) through self‐feedback structure. This structure performs complementary conversion for D‐CDS by feeding the quantized reset voltage state back to the logical feedback DFF (LF‐DFF) directly, reducing the parasitic capacitance and inner flipping nodes. The proposed counter is implemented in an 11‐bit SS‐ADC with 110‐nm CMOS process. Post‐layout simulation results indicate that compared with bitwise‐inversion (BWI) structure, the self‐feedback structure reduces power consumption by 19.5%, whereas the proposed counter achieves 27.4% power savings compared to the two‐step DDR counter. The implemented SS‐ADC consumes 15.3 W each column, with +0.4/0.6 LSB DNL, +0.9/0.5 LSB INL, and 6.4‐s conversion time, delivering a feasible low‐power counting solution for CIS.
ABSTRACT This paper presents a robust, ultra‐low‐power first‐order tunable low‐pass filter implemented in CMOS technology, specifically optimized for low‐frequency biomedical applications. Operating at a near‐threshold supply of , the proposed filter achieves a wide bandwidth tunability from to . To address the inherent instabilities of sub‐threshold operation, a novel circuit topology is employed that ensures bandwidth invariance against environmental and electrical fluctuations. Chip‐level post‐layout simulation results demonstrate an exceptionally low line sensitivity of over a wide supply range (0.5–3.0 V) and a temperature‐compensated sensitivity of only across a to range. The design maintains high signal integrity with a total harmonic distortion (THD) < 1 % for inputs up to , yielding a dynamic range. With an input‐referred noise density of and a total power consumption of only ( current drawn), the proposed filter offers a state‐of‐the‐art solution for energy‐constrained, reliable wearable healthcare monitoring systems.
ABSTRACT Differential equations and differential inequalities governing the electric power flowing along a multiconductor system with constant parameters, in stationary (DC) or in quasi‐stationary sinusoidal steady‐state (AC) regimes, are derived. A second‐order matrix ordinary differential equation (ODE), involving the power matrix and its adjoint (or transpose ), is obtained, and a fourth‐order autonomous ODE is subsequently derived for alone. In the stationary regime, the AC formulation reduces to a description of the total scalar power while in the AC regime, the active power is identified as the trace of the Hermitian part of . By passing to a modal basis, both and are shown to satisfy spectral differential inequalities—exact in the lossless or stationary cases and approximate in the weakly lossy AC regime. Systems with space‐dependent parameters are also considered. It is demonstrated that if the per‐unit‐length parameters are polynomials of maximum degree , then the power matrix satisfies a closed‐form ODE of order . Finally, it is shown that lower‐order differential inequalities for the power flow can be established by retaining terms associated with local energy densities, providing a hierarchical bounding method for non‐uniform multiconductor systems.
ABSTRACT To achieve flexible power flow allocation in distributed generation applications, an isolated dual‐active‐bridge (DAB) three‐port converter based on model predictive control (MPC) is proposed. By managing bidirectional power flow at the battery port, the converter maintains power balance among the photovoltaic (PV), battery, and load ports, with five operating modes. To extend the soft‐switching range and reduce computational complexity, an extended phase‐shift (EPS) modulation strategy with three degrees of freedom is introduced. Furthermore, a hybrid multi‐loop control strategy integrating PI and MPC is designed to coordinate inter‐port power management and enhance overall system performance. A theoretical analysis of the circuit topology, power transfer characteristics, modulation strategy, and control strategy is presented sequentially. Finally, an experimental setup is developed to validate the performance of the proposed converter under the designed control strategy. Experimental results demonstrate that the converter effectively achieves maximum power point tracking (MPPT) at the PV port and provides a stable output voltage, with the voltage THD at the AC port below 2.2%, indicating excellent steady‐state performance.
ABSTRACT This paper proposes a dual‐layer control architecture for a dual‐motor rear‐wheel‐drive electric vehicle (EV) equipped with two permanent magnet synchronous motors (PMSMs) and direct torque control (DTC). In the motor control layer, a GA‐optimized artificial neural network (GA‐ANN) replaces the conventional PI speed regulator to generate an adaptive torque‐related control signal, improving transient performance under nonlinear operating conditions. In the vehicle layer, an ant colony optimization (ACO) module computes real‐time left/right torque distributions to implement electronic differential action and enhance cornering behavior. The proposed scheme is evaluated in simulation under straight‐line driving (including road‐grade disturbance) and cornering maneuvers. Compared with conventional control strategies, the proposed approach achieves faster settling, reduced steady‐state tracking error, and improved wheel‐speed coordination during turning, resulting in improved vehicle stability and traction behavior. The results indicate that combining adaptive motor regulation with optimization‐based torque allocation provides an effective solution for EV drivetrains under variable driving conditions.
This paper introduces a high-efficiency GaAs HBT MMIC power amplifier (PA). A chip-package co-design strategy is proposed, in which high-Q bonding wires are innovatively employed to replace lossy on-chip inductors in the output matching network. This approach not only significantly reduces insertion loss but also leverages the favorable high-frequency characteristics of the bonding wires to mitigate impedance deviations at the second and third harmonics, thereby satisfying the requirements of continuous Class-F operation. The proposed theory is validated by designing a GaAs HBT PA operating from 5.9 to 7.1 GHz. The MMIC PA has a power-added efficiency (PAE) of 46%-52% with an output power of 32.9-33.7 dBm. When driven by a 20 MHz, 256 QAM modulation signal, the measured EVM is better than 1.35%. In addition, the chip area is reduced to 1.04 mm2, demonstrating that low-loss matching synthesis using bonding wires is an effective approach for realizing high-efficiency and compact RF front-end PAs.
Hardware-based methods, such as additional filters, are commonly used to suppress common-mode voltage (CMV) at the inverter output and mitigate electromagnetic interference (EMI) in permanent magnet synchronous motor (PMSM) drive systems. In this paper, a feedforward active filter based on CMV sampling and compensation is proposed. The equivalent model and transfer function of the active filter are analyzed, and the parameter design method for each filter component is derived. However, the push-pull link in a traditional feedforward active filter suffers from inherent crossover and amplitude distortions, which introduce errors between the CMV sampling and injection links and degrade the compensation performance. To address this issue, a diode-clamped push-pull structure combined with DC bias resistors is proposed. LTspice simulation results show that the improved push-pull structure effectively eliminates crossover distortion and reduces amplitude distortion compared with the traditional structure. Experimental results on a PMSM drive platform show that the improved feedforward active filter achieves a CMV peak-to-peak reduction of approximately 30% compared with the traditional feedforward active filter. Moreover, the proposed method achieves more than 10dB attenuation improvement at the fundamental switching frequency and its harmonics, verifying its superior CMV suppression capability.
Virtual inertia (VI) effectiveness in low-inertia microgrids is constrained by measurement delays introduced by phase-locked loop (PLL) synchronization. This paper investigates the delay-inertia relationship in a 37-MVA islanded microgrid and extracts an empirical, case-specific Hopf-boundary regression model, ( in seconds, over 19 boundary points). A Smith predictor-based delay compensation strategy with scheduled lead augmentation is proposed; it extends the absolute critical delay from approximately 60 ms (conventional VI) to beyond 295 ms and lifts the practical ceiling from 3 to 6 s at ms. In a head-to-head comparison against optimally detuned stable conventional VI, lead-lag-only compensation, and regression-based adaptive inertia at ms, the proposed method achieves comparable frequency nadir while reducing peak ESS power by 47%-54%; this peak-power dominance is the principal practical benefit. Under high delay-inertia combinations where conventional VI is in saturated limit-cycle operation, peak-power reduction reaches up to 72% as a separate bifurcation-avoidance benefit. Nonlinear analysis shows that conventional VI undergoes a supercritical Hopf bifurcation; the proposed compensation eliminates this bifurcation throughout the tested envelope and raises the stable-cell count of a sweep from 32% to 100%. Controller hardware-in-the-loop validation on a Xilinx PYNQ-Z2 reproduces the MATLAB Smith-predictor frequency nadir within 0.1% across four delay points and confirms sensor-noise and inertia-mismatch robustness on real hardware. Power-HIL with a real inverter, full quantitative benchmarking against MPC and , and a techno-economic study are identified as essential future work.
Traditional wireless power transfer (WPT) systems suffer from numerous drawbacks when switching between constant current (CC) and constant voltage (CV) modes, such as increasing system complexity, reducing transmission efficiency, and requiring additional detection of the battery state of charge (SOC), among other issues. To address these problems, this paper proposes a method for the automatic switching between CC and CV modes. This method eliminates the need for additional control modules, wireless communication links, and battery SOC detection, enabling automatic switching between two modes while ensuring the system operates in a zero-phase-angle (ZPA) state. Furthermore, the system features open-circuit self-protection and a high degree of design flexibility. Compared with existing solutions, the receiver side of the proposed system is more compact, making it particularly suitable for applications demanding high space utilization. To verify the feasibility and practicality of the proposed scheme, an experimental prototype with a charging current of 2 A and a charging voltage of 79 V is constructed. Experimental results validate the correctness of the theoretical analysis, and the maximum efficiency of the system reaches 95.19%.
Due to the topological symmetry of cascaded H-bridge multilevel inverters, open-circuit fault features in power switches are highly similar and susceptible to electromagnetic switching noise, significantly increasing the difficulty of fault diagnosis. This paper proposes a fault diagnosis method based on a dynamic Gramian Angular Summation Field (DGASF) and a global joint correlation attention (JCA) mechanism. A parameter-learnable adaptive DGASF mapping model is developed, in which the mapping scale and phase factors are dynamically learned via a multilayer perceptron to project one-dimensional time-domain voltage signals into a high-dimensional latent feature space. By doing so, the geometric separation between highly similar fault patterns is effectively enlarged in the feature domain. Building upon the mapped representations, a global JCA module is further introduced to exploit the physical coherence of signals through cross-channel second-order covariance statistics. In parallel, an asymmetric residual denoising path is incorporated to actively suppress endogenous switching noise that is strongly coupled with fault-related features, thereby enhancing diagnostic robustness. Experimental results show that, under extreme conditions of 40 samples per class and a signal-to-noise ratio (SNR) of 2 dB, this method can achieve a diagnostic accuracy of 79.17%, which is 9.73% higher than existing methods.
