The higher stiffness of Pb-free SAC solders makes Pb-free assemblies more sensitive to drop impact. In order to be able to optimize the drop test performance, it is necessary to have better insight into the crack propagation in the Pb-free solder joints. This study combines crack-front mapping using the dye and pry method and electrical FE simulation to establish a relation between DC electrical resistance and cracked area, and hence monitor the initiation and propagation of cracks in individual solder joints as the PCB assemblies are subjected to JEDEC type mechanical shock and high speed cyclic bending. The carrier in the study is a ball grid array (BGA), a critical component family for drop impact. Combinations of solder alloys and pad finishes, SnPb on organic solderable preservative (OSP), SAC305 on electroless nickel/immersion gold (ENIG), SAC101 on OSP, and SAC101(d) on ENIG are studied regarding the failure mode and crack propagation. This paper demonstrates that, for the large majority of Pb-free solder joints, there is a negligible initiation period; cracks can start forming at the first PCB bending cycle. The presence of large cracks, especially at both sides can increase the compliance of the joint and slow down crack growth. Even if large cracks are present, the resistance increase is less than 1 m per interconnect, which is far from the 100 that is often taken as a failure criterion. Brittle joints as found with SAC305 on ENIG have erratic propagation rates while ductile joints are much more predictable. Therefore, the way to optimize the drop test performance of a Pb-free BGA assembly is to prolong the crack propagation within the ductile bulk solder material.
We report high lateral resolution Auger electron spectroscopic (AES) measurements on high aspect ratio Sn whiskers. The whiskers were grown from compressively stressed thin films (~ 6000 Å) of Sn on brass using a magnetron sputtering system. The Auger spectra show that, after sputter cleaning, the whisker is nearly 100% Sn at all locations along the whisker shaft, at the growing blunt end of the shaft, and with depth (~ 1000 Å) into the side of the whisker. The “as received” Sn whisker surface shows the expected ~ 200 Å of native Sn oxide at all locations and the O signal nearly disappeared (~ 3 atom%) after 200 Å of sputter cleaning. There was no evidence of high amounts of oxygen within the bulk of the whisker. That brass is not observed in the whisker shaft supports the notion that whisker formation is accompanied by material mass transport through interfaces and grain boundaries which causes stress (usually compressive) relief. This is supported by the most remarkable aspect of the whisker growth; namely, that high aspect ratio Sn whiskers ~ 100-500 μm in length containing no brass can be grown from a ~ 0.6 μm thin film of Sn.
Use of lead-free solders such as Sn/Ag/Cu results in exposure of printed circuit boards to higher temperatures during assembly compared with eutectic tin-lead solder. If the thermo-mechanical and electrical properties of the laminate materials get affected by exposure to this higher temperature, that may impact the performance and reliability of the circuit board. Variations, if any, in laminate material properties before and after board assembly should be considered in the selection of appropriate laminates. The board and system designers need to be cognizant of such variations and account for them during laminate selection for an application. This paper presents guidelines for laminate selection along with the process used to derive the guidelines. The process includes measurement of key material properties (glass transition temperature, coefficient of thermal expansion, decomposition temperature, time-to-delamination, water absorption, flammability, dielectric constant, and dissipation factor), and their responses to lead-free soldering assembly conditions. A range of commercially available FR-4 printed circuit board laminate materials, classified on the basis of glass transition temperature (high, medium, and low), curing agents (dicyandiamide and phenolic), flame retardants (halogenated and halogen-free), and the presence of fillers, are included in the measurements. The measurements are conducted in accordance with IPC-TM-650 test methods before and after exposure to multiple lead-free soldering profiles. The extent of variations in the properties due to lead-free soldering exposures are reported and analyzed as a function of classification parameters. The causes behind the variations in material properties are investigated by Fourier transform infrared spectroscopy analysis and a conjunctional property analysis. This study also suggests that the preconditioning steps specified in the IPC test methods should address the initial moisture content of the laminate- - test samples in material property measurement tests, otherwise significant errors can be introduced.
In this paper, the concept of a defect phase diagram is introduced which quantifies the effects of Cu and Pb additions to electrodeposited Sn films on surface defect formation, including but not limited to the formation of Sn whiskers. Transitions were observed in both the defect densities and the morphologies of hillocks and whiskers as Cu and Pb film compositions were systematically varied. Changes in crystallographic texture were also reported for a subset of the Sn-Cu-Pb alloys examined. The transitions between different defect types and the coexistence of certain defect types help to interpret the role of grain boundary pinning in hillock and whisker formation.
Copper (Cu) ball on gold (Au) bump (COG) bonding is developed as a practicable approach to solving the challenges posed by Cu wire bonding on large integrated circuit devices. In the COG bonding, there are two different interfaces, Cu-Au and Au-Al couples, which is totally different from either Cu or Au wire bonding. In this paper, the COG bonding was studied on a typical experimental chip of 69-mu m bond pad opening and four-layer central via pattern design with current wire bonders. Tests of wire pull, ball shear, and crater were adopted in investigating the bonding strength at the interfaces and the potential damage of the underlying metals of bond pads after the COG bonding. The intermetallic compounds (IMCs) formation at the two interfaces, Cu-Au and Au-Al couples, were studied in detail on the cross-sectioned assembled samples. Two reliability tests, high-temperature baking (HTB) and temperature cycle (TC) were also used to investigate the IMC change and growth. The results showed that qualified bonding strength on all of bond pads existed and no damage such as crack and crater was observed on the underlying metals of the bond pads after removing Al metallization. At the Au-Al interface, a comparable Au-Al IMC was formed on as-bonded samples, and it gradually grew thick after the reliability tests and its corresponding content also changed along with temperature and time. At the Cu-Au interface, there was no observable formation of Cu-Al IMC on as-bonded samples. Undergoing 1008 hours HTB at 175 degrees C, only a very thin Cu-Au IMC appeared at the Cu-Au interface. After all, the Cu-Au IMC appearance hardly affects the IC's mechanical performance.
The effects of temperature and humidity on tin whisker growth were investigated through a collaborative project sponsored by the International Electronics Manufacturing Initiative (iNEMI) and its member companies. A broad range of testing conditions was adopted to test a variety of components with matte tin (Sn) plating and copper (Cu)-based leadframes. The primary goal of the study was to collect data that could be used to develop mathematical models (acceleration functions) that describe the dependence of tin whisker growth and corrosion on temperature and humidity. This paper describes the background, experimental design, data collection and reports results. Part II of the study (J. W. Osenbach et a. ?Tin whisker test development-Temperature and humidity effects part II: Acceleration model development,? Electronics Packaging Manufacturing, Vol. 33, no. 1, pp., Jan. 2010) discusses in the data analyses and acceleration model development. Storage testing was performed over a wide range of temperature and humidity conditions from 30?C to 100?C and from 10% to 90% relative humidity (RH). Commercially produced components with both 3 ?m and 10 ?m thicknesses from three sources were evaluated. For components with the 10 ?m-plating, the plating was evaluated in both the as-plated and reflowed (260?C) conditions. These variations resulted in a large experimental matrix that included 13 different Sn platings, aged at ten different temperature and humidity combinations. Further, the aging test was done at five different laboratories with inspections performed at eight different laboratories. The data collected include 1) corrosion incubation time, 2) tin whisker incubation time, and 3) dependence of the maximum whisker length on storage time at each temperature/humidity condition. Data suggest that corrosion is not a unique driving force for whisker initiation and growth. Whisker formation differs in corroded and non-corroded regions. Due to the scope of this work, it is broken down into two papers. The data and experimental observations are discussed in this paper. The mathematical model development, discussion of results and conclusions are included in Part II of this study.
Die bonding in the semiconductor industry requires placement of solder bumps not on PCBs but on wafers. Such wafer bumps, which are much miniaturized from their counterparts on printed circuit boards (PCBs), require their heights meet rigid specifications. Yet the small size, the lack of texture, and the mirror-like nature of the bump surface make the inspection task a challenge. Existing inspection schemes generally reconstruct every bump surface. This work addresses by how much can the task be simplified if merely the bump heights are inspected against the specification. It is assumed that ball bumps are used as the wafer bumps. An imaging setup is described that lets the peaks of the ball bumps be distinguishable in the image data. A measure is also described that reveals how well the ball bumps meet the height specification without going through explicit 3-D reconstruction. The measurement, in the form of a 3 × 3 matrix extractable from the image data, is sensitive to variations in the bump heights, but not to 2-D uncertainties in soldering the bumps onto the wafer substrate, or small variations in the placement of the wafer in 3-D. Experimental results are shown to illustrate the effectiveness of the proposed system.
To reduce manufacturing cost, lead time, and process complexity, an embedded-active approach that targets rapid prototyping and low-volume production in micro-system packaging is being developed. The approach involves a rapid prototyping of micro-system packaging by a data-driven chip-first packaging process using direct printing of nano-particle metals. In the chip-first process, bare dice are first embedded into a copper or stainless steel carrier substrate, fixed by filling the gap between the chips and the substrate with thermoplastic adhesives, and planarized to a common planar surface. On the coplanar substrate, polyimide film is laminated to form a dielectric layer. Through the dielectric layer to the chip metal pads, micro vias are drilled by laser ablation. The vias are filled with nano-particle silver (NPS). The NPS is deposited by screen printing or aerosol-jet printing and an electrical circuit is formed. This packaging approach is a dry process and it does not require any photo masks for circuit patterning, resulting in reducing packaging turn-around time from months to days. It is also less limited by substrate composition and morphology, eliminates the need for special chip processing such as flip chip solder bumps, and permits using any chip technology and any chip supplier allowing mixed devices. The embedded-active process with NPS avoids the extreme processing conditions required for standard IC fabrication such as wet chemistry processing and vacuum sputtering. The NPS can be sintered at plastic-compatible temperatures as low as 230?C to form material nearly indistinguishable from the bulk metal. The embedded-active packaging shows good reliability performance in terms of thermal shock, which is performed in the range of -40?C and 125?C. These results represent an important step to a system packaging characterized by high-density, low-cost, and data-driven fabrication for rapid package prototyping. This paper presents details of the rapid prototyping process sequence, an initial reliability characterization of the package architecture, and a failure mode analysis of the packages.
Copper (Cu) wire-bonding with its advantage in cost, mechanical enhanced characteristic, and better electrical performance is a developing alternative interconnection technology to replace gold (Au) and aluminum (Al) wires in IC packaging manufacturing. This paper discussed the experimental study of using 6-mil Cu wire on an ASM wire bonder to replace 10-15 mil Al wire in a power IC device. It encompassed wire and tool selection, wire-bonding process development, post wire-bonding integrity inspection, and bonding reliability results. The wire and tool selection included type of wire, capillary use, and bonder capability. The process development focused on two crucial stages, Free air ball (FAB) formation and bonding process window development. Design of experiment (DOE) was extensively applied in this study. The experimental studies showed that flow rate of forming gas was a key factor to form the qualified FABs and establishment of a workable process window. Wire pull and ball shear tests were conducted per JEDEC criteria for bond strength integrity. Moreover, crater test and Zygo's 3-D measurement were used to inspect any risk of underlying metal integrity in die before reliability tests. The data showed that sufficient thickness of the Al bond pad was crucial to avoid any underlying metal damage when subjected to heavy copper wire bonding forces. High-temperature baking (HTB) and pre-condition (PC) and temperature cycle (TC) were used to evaluate the samples reliability. The results of the two reliability tests showed that Cu/AL intermetallic compound (IMC) growth was slow, which indicates potential significant product life-span extension. The study concluded that with current thermosonic ball bonder, using 6-mil Cu wire could replace heavy 10-15 mil Al wire in power IC applications.
The seven papers in this special section focus on research related to tin whisker growth and mitigation.
This paper discusses the electric performance for thermosonic wire bonding of gold wire onto copper pads. Various methods normally used to improve bondability were investigated including the bare copper pads with argon shielding gas and the copper pads with cupric oxide film, cuprous oxide film, and silver film. The micro-contact theory was used to determine the effective contact area. The circuit contact resistance was measured for each sample and was presented in terms of ultrasound power and effective contact area. The results show that the increase in the effective contact area leads to a lower circuit contact resistance before reaching a minimum value, and further increase in the effective contact area would not have noticeable effect on the resistance.
We develop an evolutionary method of planning paths that are subject to subpath constraints. These constraints can include subpaths that must be incorporated into the solution path, path intersection restrictions, and obstacle avoidance. Our method involves two stages. In the first stage, a global solution is found without consideration of any obstacles. In the second stage, local planning is performed to modify the global path to avoid obstacles. Stage one involves a fixed-length chromosome formulation of a genetic algorithm that utilizes existing operators and a new subpath reversal operator. Stage two involves a graph search process. Our algorithm is applicable to the field of printed electronics where continuous-spray processes are used to deposit electrically functional material onto flexible substrates. These processes give rise to the kinds of subpath constraints we have investigated. We evaluate our algorithm by applying it to a representative problem in the printed electronics field.
Increased functional density and reduced input/output (I/O) spacing are the market trends in the electronics manufacturing industry. Industry reports indicate that approximately 50%-70% of soldering defects are attributed to the solder paste printing process for printed circuit board (PCB) assembly. Hence, after the printing process, a solder paste inspection (SPI) system is generally used to examine the amount of solder paste deposition. Effective selection of components and bonding pads during solder inspection is extremely important in achieving desired process cycle times and ensuring assembly yield. This paper uses the Mahalanobis-Taguchi system to establish a systematic approach to determining guidelines for solder paste inspection. Among a total of 203 bonding pads on the board for a GPS product, the optimal model suggests that the solder deposition of 121 bonding pads be inspected. The reduction ratio is 40.4%, and the feasibility of the proposed model is verified. Also, for those bonding pads to be inspected for their solder paste deposition, this study uses empirical data to define the specifications to effectively distinguish acceptable PCB samples from defective. The threshold is within the 100% capability for judgment of solder paste printing quality in the surface mount assembly process.
Along with the technology advance, the applications of flip chip have the tendency toward lower profile, lighter weight, and higher density. Due to the mismatch of the coefficients of thermal expansion (CTE) between the chip and substrate, the solder joints tend to fail under high thermal stresses. In order to enhance the reliability of the solder joints, underfill encapsulation is filled into the gap between the chip and substrate around the solder joints by capillary force. It is crucial for flip-chip technology to speed up the encapsulation process and avoid the formation of voids at the same time. A finite-element model was developed to simulate the underfill flow in our laboratory. In this paper, further verification of the underfill model is performed to confirm its feasibility. A model is proposed to design an efficient process for encapsulant dispensing based on the underfill model. Application of the model is also conducted to investigate the effect of different bump designs on the dispensing process.
In this paper, characterization methods are presented with results from test structures printed with varying printing parameters and materials. It is shown that different process parameters affect both physical and electrical material properties and hence high-frequency material characterization is a vital part of the process providing important information for design purposes. The conductivities and loss information of nanoparticle inks and properties of dielectric material are achieved in addition to structural properties. In particular, dc measurement results from 1.1e7 S/m to 3.7e7 S/m and high-frequency attenuation values from 0.5 dB/cm to 2.8 dB/cm (at 10 GHz) are achieved for printed conductors.
We have developed a new etching solution for the printed circuit board industry. The primary oxidant of the solution is nitric acid, which reacts with copper coating on the substrate. The other components of the solution are sulfuric acid and additive, which are used to control etching reaction rate and solution's characteristics. The optimum parameters for the concentrations of nitric acid, sulfuric acid, additive, and the operating temperature were obtained through orthogonal experiment with stagnant etching method. The parameters were then verified by the spray etching experiment in the industrial production line. Then, there are a series of tests, carried out by metallographic slicing tester and scanning electron microscopy to evaluate the quality of copper conductive lines in stagnant and spray etching experiments. compared with conventional cupric chloride etchant, the testing results showed that the nitric acid etchant can manufacture fine lines with lower undercut, better wall sides, with higher etching rate, as well as being more friendly to the environment How the addition of H2SO4 influences etching rate and etching mechanism of nitric acid etchant is also discussed.
This paper considers the influence of 1) humidity and 2) acidic humidity on the growth of Sn whiskers. Sn whisker morphology was observed over a six-month period. The results show that the electroplated surfaces exposed to pure humidity are populated with Sn whiskers dimensionally smaller than surfaces exposed to acidic humidity. Variables analyzed include surface condition, Cu-Sn inter-metallic formation at the film/substrate interface by X-ray Diffraction (XRD), and film thickness.
Roll-to-roll (R2R) gravure printing is considered to be a leading technology for the production of flexible and low-cost printed electronics in the near future. To enable the use of R2R gravure in printed electronics, the limits of overlay printing registration accuracy (OPRA) and the scalability of printed features with respect to the physical parameters of the gravure system, including given plastic substrates and inks, should be characterized. Important parameters of printed lines include surface roughness, thickness, line widening, and line-edge roughness. To date, there are no comprehensive reports regarding the limits of OPRA and the scalability of printed electrodes, including the control of surface roughness, thickness, line widening, and line-edge roughness using R2R gravure printing. In this paper, we examine ways of evaluating the OPRA limit of our gravure system. We find that OPRA is limited in the web moving direction to 40 μm and in the perpendicular direction to 16 μm, showing the importance of web handling on registration. Furthermore, we demonstrate the scalability of printed electrodes formed using a R2R gravure system to linewidths of 317 μm, with 440 nm thickness, 30 nm of surface roughness and edge waviness of 4 μm on PET foils, and describe optimization strategies to realize improved surface roughness, thickness, line widening, and line-edge roughness for future printed electronics applications.
When a tin whisker bridges two differently biased conductors, an electrical short is not guaranteed. In many instances, the voltage must exceed a threshold level in order to produce current flow due to weak physical contact and the presence of a non-conductive film such as an oxide layer. This paper presents a study that examines the breakdown voltage of tin whiskers and its relation to contact force. Whisker contact force studies were conducted using gold- and tin-coated tungsten probes, and the breakdown voltage was measured using a semiconductor parameter analyzer. It was verified that contact force is a critical factor in determining the type of current-voltage transition and level of breakdown voltage. Lower contact force between the probe and the whiskers caused the multiple transitions in current-voltage characteristics. The tin oxide layers on whiskers were analyzed using field emission transmission electron microscopy (FE-TEM).
The incubation time for both whisker growth and corrosion in thin Sn platings (3-10 ¿m thick) on Cu-based alloys have been found to be well represented by an exponential function of humidity and an Arrhenius function of temperature for both as-deposited and reflowed tin platings. Furthermore, whisker growth was found to follow the same functionality in both corroded and non-corroded regions of the plating. The effective activation energies and humidity coefficients were found to depend upon plating thickness, exposure to reflow, and presence of corrosion. The effective activation energies ranged from 0.23 eV to 0.41 eV and the humidity coefficients ranged from -0.012% to -0.031%. Corrosion enhanced whisker growth occurred by lowering the effective activation energy for whisker growth. A theory based on excess, non-creep relaxed, oxidation induced strain was developed to explain the corrosion induced energy barrier lowering. The data showed that 60°C/87%RH appears to be the optimal high temperature/high humidity test condition at this time for Sn over Cu substrates. Within the limits of the whisker and corrosion (incubation) acceleration functions developed in this study, it is concluded that the JEDEC tests can be used to indicate behavior at other temperature/humidity points that could be relevant storage or service conditions.
