This research provided the latest development of sintered silver (Ag) and copper (Cu) as die-attach materials based on the patent data retrieved from www.lens.org using the two criteria of patent claims of “silver” or “copper”, “sinter*” and cooperative patent classification (CPC) of H01L2224/8384 (die-attach application with sintering technique). Based on these two criteria, the patent filing trend of sintered Cu mirrored those of sintered Ag, including the peak in 2015. Closer data inspection revealed that this mirroring reflected the patent claims technique, which included Cu and Ag, and sometimes other elements, such as gold, nickel, palladium, aluminium and platinum, as metal particles to be sintered for die-bonding applications. At the same time, patents that claimed either the Cu or Ag exclusively for their paste formulation or used these sintered joints as part of the microelectronic packaging designs, were also available, but generally restricted to sintered Ag joints. However, the obviousness or “equivalences” between sintered Cu and Ag in the patent prosecution process might pose a problem in patent infringement cases, but none had been reported. In addition, other “valuable” patents based on patent family size and forward-citations counts, were also identified and discussed in developing these sintered metal technologies. In conclusion, the rapid development of sintered Ag and Cu as die-attach joints in the microelectronic packaging industry, especially among power module manufacturers, had matured in their technology life-cycle, based on the patent filing data.
In conventional semiconductor machine operation method, it is required the operator physically to be in front of the machine. The operator needs to walk from one machine to another machine just to make the machine run. Without operator, the machine cannot run smoothly especially if there are many machine stoppages. Because of this issue, the engineer needs to work on how to reduce the machine stoppages and improve the machine performance. In certain circumstances, the machine has a limitation, and the machine stoppages cannot be improved anymore especially to the old machine generation. To maintain the old machine generation performance is very challenging and sometime the machine spare part is also obsoleted. By introducing the remote system in the semiconductor, it will help to solve the machine limitation issue. From the control room, the operator able to clear the machine stoppages without physically need to be in front of the machine. It will help to reduce operator workload, reduce the machine downtime, improve the man-to-machine ratio and at the end reduce the cost. Fig. 1 below shown the comparison between with and without remote system. The number of operators can be reduced significantly, and the movement of the operator also can be reduced. Bear in mind, not all the machine stoppages can be remoted. The remote system also has its own limitation. For example, change material, change lot, and change the machine part cannot be done remotely. Its still require operator physically to be in front of the machine.
Ultra-fine SAC305 solder is widely used as lead-free interconnection in advanced packaging because of its advantages such as good joint strength, thermo-mechanical fatigue behavior and creep resistance. Stencil printing remains the technology of choice for assembling because of its ease of process control, flexibility of usage, wider process window, and economic usage. Advanced package involves integration of different components, copper (Cu) pillar, flip-chip devices, and chips in one package to achieve multiple functions in one system. The need to accommodate ever increasing demands for reduced footprints requires constant inventions of flip chips with Cu pillar diameter of $\mathbf{55}\boldsymbol{\mu} \mathbf{m}$ and smaller. Many mobile communications consist of 6 or more flip chips in a single package. Conventional flip-chip attach uses flux and Cu pillar solder cap for interconnect formation, it is a challenge to print solder paste of fine geometries below $\mathbf{70}\boldsymbol{\mu} \mathbf{m}$ . Heraeus's solder paste makes use of ultra-fine spherical shaped solder powder (T7 particles size) to create strong metal coalescence for bonding during reflow process of Cu pillars onto substrates. Reduction in flip-chip Cu pillar diameter to $\mathbf{55}\boldsymbol{\mu} \mathbf{m}$ requires further reduction in stencil opening to $\mathbf{55}\boldsymbol{\mu} \mathbf{m}$ , thus limiting the usage of T7 paste. Present study reports stencil printing application of new version of T7 solder paste with reformulated flux system. The application evaluations using $\mathbf{55}\boldsymbol{\mu} \mathbf{m}$ stencil opening (SO) revealed good results by successfully printing $\mathbf{35}\boldsymbol{\mu} \mathbf{m}$ line spacing (LS) without defects such as bridging, missing & inconsistent dots. It also achieved average paste release volume of ~30% up to 12hours of continues printing.
This paper reports on the advanced assembly technology for small chip size of Fan-out WLP(FO-WLP) using high expansion tape. In a preceding paper, we reported that we have developed new tape expansion machine which can expand tape in four directions individually. Using this expansion machine device, we have developed high expansion tape which can get enough chip distance after expansion. Our expansion technology provides both high throughput and high placement accuracy. These previous studies have been evaluated using 3 mm x 3 mm chips assuming an actual FO-WLP device. Since our process can be handled by wafer size, smaller chip size improves throughput than larger chip size. In this study, we evaluate with 0.6 mm x 0.3 mm chip size and investigate tape characteristics required for small chip size expansion. By optimizing adhesive thickness and composition of adhesive, we succeed in developing high expansion tape for small chip size with good expandability and no adhesive residue on the expanded chip. We indicate that our proposal process is also effective for small chip size of FO-WLP.
The major technology shift on the horizon to 5G, autonomous vehicle, and AI have driven semiconductor industries to strive for the continuous development of electronic devices with better functionality and higher power efficiency. Ultra wafer thinning process appears to be one of the promising solutions to produce semiconductor chip with lower resistance and hence better electrical performance. Apart from electrical performance, it is very important to understand the mechanical properties of the ultra-thinned silicon chip. Different wafer back-grinding, stress relief etching and metallization steps in wafer thinning process flow will determine the die strength, surface condition, and reliability of the semiconductor chip. When wafer becomes thinner, it becomes more susceptible towards stress induced failures such as wafer saw chipping and die crack during assembly process. Also, a correlation is found between the wafer back metal surface roughness and solder die attach performance. In this study, wafers were processed with several ultra-thinning process flow that involves different etching method and metallization. The mechanical and surface properties of the wafers were then characterized to identify the correlation between the resulted properties and thinning process flow. In order to enhance the reliability and robustness of the final semiconductor package, it is very crucial to understand the effect of wafer back metal thickness and surface roughness of ultra-thin wafer towards backend assembly processes.
