Cyclic Queuing and Forwarding (CQF) is an increasingly adopted mechanism in Time-Sensitive Networking (TSN) for bounding end-to-end delays through fixed-length cycles with alternating transmission queues. While timing guarantees for CQF flows are well established under both time-triggered (TT) and event-triggered (ET) implementations, the worst-case interference that CQF may impose on other traffic classes in mixed-criticality TSN networks remains an open problem. This challenge is exacerbated by the structured, non-work-conserving behavior of CQF and the complexity of its interaction with heterogeneous TSN scheduling mechanisms such as TAS, CBS, and SP. This paper presents the first formal framework for quantifying the worst-case interference caused by CQF on other schedulers under both TT- and ET-based implementations. We propose a network-calculus-based CQF real-time interface abstraction that models the residual service available to coexisting traffic. We formally derive closed-form upper bounds on CQF-induced interference, explicitly capturing bidirectional interactions between CQF and both higher- and lower-priority traffic classes. These bounds can be modularly and seamlessly integrated into existing schedulability analyses, enabling scalable and compositional timing verification in hybrid TSN architectures. Extensive evaluations on synthetic benchmarks and realistic TSN configurations demonstrate the analytical effectiveness, scalability, and practical applicability of the proposed framework in certifying end-to-end guarantees in mixed-criticality TSN systems.
Time-Sensitive Networking enables deterministic communication in cyber-physical systems using time-aware shapers governed by Gate Control Lists (GCL). Although this mechanism improves reliability, it also introduces vulnerabilities exploitable through schedule-based attacks. We show that, by analyzing traffic patterns, adversaries can estimate GCL parameters and reconstruct the schedule to inject precisely timed traffic. These injections can cause priority inversions, where low-priority flows delay high-priority traffic, degrading latency and schedulability. Such schedule-based attacks are particularly stealthy as conventional Intrusion Detection Systems (IDS) may fail to detect them. We implement this attack and conduct randomized experiments to evaluate the impact on synthetic workloads and on off-the-shelf hardware.
Deploying large language models (LLMs) on edge devices enables real-time responses while preserving user privacy. However, constrained memory and compute resources pose significant challenges for high-quality, single-device inference. To address this, we propose HCInfer, a hierarchical coordination framework for collaborative LLM inference across edge devices. By leveraging idle neighboring devices, HCInfer alleviates performance bottlenecks typical in isolated deployments. HCInfer employs a two-level coordination strategy. At the inter-device level, it leverages idle neighboring devices to collaboratively process attention computations, significantly reducing synchronization overhead. At the intra-device level, it applies finegrained memory and compute optimizations to fully exploit local hardware capabilities. Building on this architecture, HCInfer integrates three key components: (1) Asymmetric Transformer decomposition decouples attention and FFN computation, enabling selective and parallel execution across devices. (2) Layer-wise subdeadline scheduling dynamically profiles execution latency and adapts precision or structure to meet real-time constraints (3) An Overhead Mitigation Module efficiently manages on-device resource usage to support scalability without overwhelming hardware. We evaluate HCInfer on PC, smart home, and mobile platforms using OPT-13B, Qwen2.5-14B, and Llama2-13B models. Experiments show HCInfer achieves 1.67x to 4.3x speedup in TTFT and 1.16x to 17.15x speedup in TPOT compared to existing baselines, maintaining a sub-deadline miss rate (SubDMR) of 15.3% under worst-case conditions while keeping model accuracy degradation within 8% for typical cases and up to 11% in extreme scenarios. These results demonstrate HCInfer's potential to enable efficient and responsive LLM inference in real-world edge environments.
As industrial control applications scale up, mesh networked control systems (MNCSs) are gaining popularity, where multiple control loops share a multi-hop mesh network. However, these loops often suffer from long-span, time-varying delays caused by the multi-hop transmissions of multiple flows, which significantly degrade control performance, particularly stability. Existing studies on delay-aware stability conditions are usually independent with network scheduling, leading to a pessimistic stability analysis. Meanwhile, existing stability-aware scheduling approaches rely on coarse-grained designs, further worsening stability guarantees and limiting network capacity. In this work, we propose a stability-guaranteed scheduling mechanism for MNCSs with fine-grained timing. We first establish a stability condition that accounts for time-varying delays over an extended horizon spanning multiple superframes, which reduces the pessimism in stability analysis and enables more refined scheduling strategies. Based on this condition, We design a Long time-horizon and Fine-grained network scheduling mechanism with Stability Guarantee (LFSG), which deterministically maps the stability condition into the fine-grained network scheduling, considering fluctuating delays over the extended horizon. Furthermore, we provide a stability-capacity-aware LFSG (SCA-LFSG), which aims to maximize the number of stabilizable control loops and demonstrates its effectiveness through various application paradigms. Extensive studies demonstrate the advantages of stability analyses, LFSG, and SCA-LFSG over state-of-the-art approaches in terms of both control and timing performance.
Weakly-hard real-time systems enhance resource efficiency by allowing bounded deadline misses, but practical support in existing platforms remains limited. In this work-in-progress, we present the CBS-based Weakly-Hard Framework, which maps tasks with $(m, K)$ constraints into Constant Bandwidth Server (CBS) parameters under the SCHED_DEADLINE policy in Linux. The proposed approach requires no kernel modifications and guarantees schedulability through constrained-deadline EDF analysis. We implemented the framework as a user-space API and evaluated it on a Raspberry Pi platform. Experimental results show improved schedulability compared to existing methods and demonstrate potential opportunities for Quality-of-Service (QoS) enhancement.
Consensus algorithms are widely adopted in clustered systems to distribute data efficiently, with Raft being a prominent failover algorithm due to its effectiveness and fault tolerance. However, Raft and other consensus algorithms do not provide timing guarantees, limiting their application to time-critical systems such as industrial control systems, drone swarms, and autonomous vehicle networks, where it is critical to distribute state machines in time and prevent multiple timing misses of data. In this paper, we propose CARTEL (Consensus Adapting Real-Time and Efficient Logging), a novel consensus algorithm that integrates time-predictability into the Raft framework. To achieve this aim, we examine Raft's mechanisms and identify the characteristics that impact the timing of data propagation within a distributed system. Based on these insights, we design CARTEL by developing two mechanisms that address the primary limitations of Raft: (i) CARTEL voting to solve the uncertainty of leader election timing, and (ii) CARTEL node buffer to limit the number of indeterminately deferred data during leader failure. Moreover, we propose how to utilize the mechanisms of CARTEL to ensure time-predictability in leader elections and mitigate the indeterminate nature of data logging during leader transitions, without harming the integrity of Raft. We validate the effectiveness of CARTEL through real-world implementation. The experiments confirm that CARTEL not only reduces the uncertainty of system recovery inherent in the election process (by 65.7% compared to Raft) but also enhances the integrity of the distributed system by guaranteeing timely data logging.
Partitioning kernels often face challenges such as static resource allocation and insufficient temporal protection, limiting their applicability in dynamic and mixed-criticality systems where resource needs and security boundaries evolve over time. To address these limitations, we present S3K, a capability-based multicore partitioning kernel for embedded RISC-V systems. S3K provides robust spatial and temporal isolation, time protection, and dynamic resource reconfiguration, enabling flexible adaptation to changing operational requirements while maintaining strong safety and security guarantees. Its capability-based model ensures secure and efficient resource management, while in-kernel data partitioning prevents information leakage and mitigates side-channel attacks. Additionally, S3K's scheduler guarantees deterministic process dispatch, free from microarchitectural interference. Evaluation results demonstrate S3K's effectiveness, showing the absence of scheduling jitter, resistance to intra-core side-channels, and efficient interprocess communication. These results highlight S3K's suitability for safety-critical and security-critical applications in dynamic, resource-constrained environments.
Modern real-time workloads are often expressed as processing graphs that have complex dataflow dependencies. No scheduling algorithm with a holistic analysis of graph-based tasks is known that can provide bounded response times without utilization loss, thus ensuring soft-real-time optimality, when a node instance depends on some of its prior instances and multiple invocations of the same graph can be active simultaneously. This paper presents a scheduling policy for such a graph-based task and provides a response-time analysis that guarantees bounded response times without utilization loss. Experimental evaluations show that our scheduler yields significantly tighter response-time bounds than existing soft-real-time optimal schedulers.
IEEE 802.1Qbv Time-Aware Shaper (TAS) is a cornerstone of Time-Sensitive Networking (TSN), offering bounded latency and near-zero jitter for critical traffic (CT). However, prior scheduling algorithms either rely on ideal clock synchronization or resource reservation, sacrificing bandwidth efficiency. In this paper, we present a unified framework for the analysis of stability for queueing process and delay bounds in TAS, in which clock drift, gate-switching jitter, and sync-message loss are modeled as a stochastic service-loss process in TAS scheduling. Then, a Lyapunov-drift analysis is used to derive both deterministic worst-case delay bounds under maximal service loss and probabilistic stability conditions when the average service rate exceeds the arrival rate. Finally, based on the theoretical analysis, the guard-band sizing and slot-provisioning guidelines are proposed for practical TSN deployment under non-ideal synchronization. Extensive simulations have been conducted to validate the tightness of our delay bounds, and the simulation results demonstrate that the proposed configuration rules can guarantee bounded latency and queue stability.
Ensuring timely task execution in multiprocessor systems under Global Fixed-Priority Scheduling (GFPS) remains a significant challenge. While traditional heuristic methods often struggle to derive feasible priority assignments for complex task sets, existing Deep Reinforcement Learning (DRL) approaches—though more powerful—suffer from two key limitations: (1) they fail to adequately capture relative priorities among high-priority tasks during encoding, and (2) their convergence to suboptimal policies due to sensitivity to local reward signals, an inherent drawback of reinforcement learning frameworks. To overcome these issues, we propose PAGFN, a novel learning-based framework that combines Priority-Aware Attention with Generative Flow Networks. We formulate the priority assignment problem as a Markov Decision Process (MDP) and employ an encoder-decoder architecture with auto-regressive decoding. Our framework introduces a priority-aware module to explicitly model task dependencies, enhancing assignment quality. Additionally, to mitigate sparse rewards, we integrate expert pretraining and prioritized experience replay, enabling diverse policy exploration without relying on intricate reward shaping. Experimental results on synthetic tasks show that PAGFN outperforms heuristic and learning-based baselines, particularly in scheduling previously unschedulable tasks, validating its effectiveness and scalability.
Reproducing and extending research on TimeSensitive Networking (TSN) scheduling has become increasingly challenging, as most published methods lack open-source implementations. The few available implementations are often scattered across different programming languages and formats, forcing researchers to reimplement algorithms from scratch—a time-consuming and error-prone process that hinders fair comparison of methods and slows research progress. In this work, we present TSNKit, an open-source toolkit designed to address these challenges through: (i) standardized implementations of a broad set of representative scheduling algorithms with unified interfaces for integrating new methods; (ii) an end-to-end pipeline covering test case generation, scheduling, and simulation-based validation; and (iii) comprehensive benchmarking modules for reproducible performance evaluation. TSNKit enables researchers to reproduce published results, extend existing methods, and perform fair comparisons across algorithms. Our ongoing work extends TSNKit to support multiple traffic shapers beyond Time-Aware Shaping (TAS), improve benchmark efficiency through enhanced scheduling heuristics, and incorporate hardware-in-the-loop capabilities for seamless real-world deployment.
Timely observation of transient astrophysical phenomena (TAP) is of crucial importance for our understanding of the universe and the laws of physics, as recognized by the National Academies in the Astro2020 decadal survey. Ultimately, the goal is to observe TAPs as early as possible using optical telescopes. This is non-trivial due to the probabilistic nature of the search problem, where multiple potential sky locations for a TAP, each with an associated probability, must be scheduled for observation before successful localization. The problem lies at the intersection of several research disciplines, including realtime systems, cyber-physical systems, astrophysics, and operations research, motivating the need for a unified modeling framework. To this end, we introduce the first formal stochastic, response-time-aware model for search planning toward detection and localization of TAPs. We consider the problem of maximizing expected utility of early localization and show that it is reducible to the Orienteering Problem. Building on this formulation, we develop the real-time-capable Greedy-Christofides Pathfinding (GCP) algorithm. An evaluation on 37 probability maps from LIGO demonstrates that GCP consistently achieves high solution quality and computational efficiency across diverse search scenarios. GCP achieves = 0.5% deviation from the ILP-computed optimal solution on tractable problem instances while running within a second, on average, for larger inputs.
This paper presents an open-source kernel-level heterogeneous memory characterization framework (MemScope) for embedded systems. MemScope enables precise characterization of the temporal behavior of available memory modules under configurable contention stress scenarios. MemScope leverages kernel-level control over physical memory allocation, cache maintenance, CPU state, interrupts, and I/O device activity to accurately benchmark heterogeneous memory subsystems. This gives us the privilege to directly map pieces of contiguous physical memory and instantiate allocators, allowing us to finely control cores to create and eliminate interference. Additionally, we can minimize noise and interruptions, guaranteeing more consistent and precise results compared to equivalent user-space solutions. Running our Framework on a Xilinx Zynq UltraScale+ ZCU102 CPU-FPGA platform demonstrates its capability to precisely benchmark bandwidth and latency across various memory types, including PL-side DRAM and BRAM, in a multi-core system.
Emerging cyber-physical systems have embraced a large number of IoT devices spanning geo-distributed, which generate and consume massive volumes of data continuously. Accurate and timely spatiotemporal predictions (STP) over these streaming sensor data are critical and, in growing demand, ubiquitous across various edge scenarios such as traffic flow forecasting. Towards that, recent advanced systems have developed sophisticated optimizations among STP pipelines, aiming at optimal prediction performance. However, based on our empirical studies in real-world settings, we identify a previously overlooked bottleneck of end-to-end STP performance: data staleness. To mitigate this issue, in this work, we investigate a new task, namely stream interception, which deliberately terminates the acceptance of incoming sensor data and anticipates model execution with imputed missing features. We propose a novel dynamic interception strategy to determine the time slot to exit waiting and present Grape, an STP system that implements it with practical system designs. Extensive evaluations on real-world traces show that Grape can strike a superior tradeoff between prediction accuracy and serving latency, achieving 1.69-1.90x speedup against traditional all-waiting baselines across various STP services with high prediction accuracy on par with offline optimal cases.
The Robot Operating System 2 (ROS 2) has become a widely adopted middleware framework for building modular and distributed robotic systems. Its intra-process communication mechanism is designed to reduce latency by avoiding serialization and memory copying, which is often treated as a negligible or constant-cost operation in both system design and performance analysis. However, this assumption oversimplifies the underlying behavior and may lead to inaccurate performance models and misleading conclusions, especially in latency-sensitive applications. In this paper, we present a comprehensive analysis of intraprocess communication in ROS 2, revealing that its performance is highly sensitive to message configuration, workload structure, and message usage strategies. We identify a scalability risk caused by misaligned communication configurations and propose a guideline to ensure efficient and predictable intra-process communication across varying execution patterns. In addition, we uncover a performance bottleneck in the default ROS 2 implementation stemming from repeated message creation. To address this, we propose a novel message pooling mechanism that reuses message objects to exploit temporal locality and eliminate redundant allocations. Our design is fully compatible with existing ROS 2 APIs and requires no modifications to application-level code. Experimental evaluations using synthetic benchmarks and real-world case studies demonstrate substantial improvements in communication latency, validating the practicality of our design.
Real-Time Embedded Systems (RTES) are widely used in safety-critical devices, where deterministic data flow is essential to system verification and reliable execution. It requires that each consumer task instance reads data from the deterministic producer task instance. In software based on general-purpose computing instruction sets, communication-related instruction execution order couples data flow among tasks, necessitating a deterministic execution order of these instructions to preserve data-flow determinism. However, enforcing this order complicates software, and suffers from priority inversion and variable execution overheads, which significantly increases task worst-case response times (WCRT) and response time variability. This paper identifies the cause of above issues as the semantics of general-purpose instruction sets, under which dataflow determinism relies on the deterministic execution order of communication-related instructions. To address this, we make the following contributions. First, we propose Time-Semantic Instruction set (TSI), which supports memory access using both addresses and timestamps. TSI enables data-flow determinism without strict instruction ordering. Second, we design a TSI-enabled implementation compatible with conventional memory systems. Third, we provide two TSI-based deterministic dataflow programming paradigms, along with correctness proofs. Finally, we evaluate TSI hardware cost and implement a cycle-accurate simulator based on a TSI-extended RISC-V. Experiments demonstrate that, under reasonable memory overhead, our approach reduces programming complexity and achieves up to 21.6x reduction in WCRT and up to 89.6x reduction in response time variability compared to existing methods.
Multicollinearity of Event Monitors (EMs) negatively impacts the modeling of non-functional critical metrics in real-time systems like worst-case timing and energy usage since some EMs are over-represented and can reduce model accuracy. To address this challenge, we propose Event Monitor Reduction (EMR), a method to select a reduced set of non-related (independent) features (EMs), hence eliminating multicollinearity. In particular, EMR finds linear relations between the EMs and removes dependent ones without data loss. EMR does not create new features like Principal Component Analysis does, simplifying interpretability. Results on synthetic data and data collected from the execution of representative benchmarks on an avionicsgrade processor show the benefits of our method in removing multicollinear EMs. We further illustrate the benefits of EMR on two different multicore timing contention models, showing how its application helps to reduce execution time requirements and increase the accuracy of the models.
Worst-case timing analysis traditionally begins with estimating the worst-case execution time (WCET) of individual tasks using either static analysis or measurement-based techniques. To derive worst-case response times (WCRTs), engineers typically compose these WCETs with bounds on preemption and operating system overheads. However, WCRTs depend on complex system-level interactions, including task communication, OS behavior, and asynchronous events. Compositional analysis often overestimates, assuming that worst-case conditions across components coincide, admitting infeasible global control-flow paths. Static whole-system techniques refine this by modeling the system holistically but require platform-specific tailoring or extensive annotations. A dynamic equivalent has been missing. We present FRET, the first dynamic whole-system approach for estimating WCRTs. FRET employs feedback-guided fuzzing to uncover timing-critical dependencies, including inter-task communication, task/OS interactions, and interrupt effects, without requiring prior knowledge of inputs or states. Implemented using LibAFL and evaluated on FreeRTOS with realistic benchmarks, FRET consistently outperforms state-of-the-art fuzzing strategies in estimating accurate response times. Although not sound, FRET delivers more than timing estimates: it produces actionable artifacts-worst-case inputs, interrupt schedules, and inter-task program-flow information-that complement static analyses and support system validation, runtime monitoring, and robust mixed-criticality scheduling.
Emerging embedded systems have to increasingly meet energy constraints besides their timing requirements. While frequency-scaling techniques are well explored, existing operating systems for embedded real-time systems have shortcomings in comprehensively exploiting energy-saving features present in modern system-on-chip (SoC) platforms. Existing systems lack operating-system abstractions to exploit the tradeoff between computing performance and energy efficiency. Consequently, whole-system analysis techniques are not applicable to yield optimal configurations tailored to the applications' requirements. Finally, the complexity of modern energy-saving hardware features creates huge search spaces for optimal configurations. In this paper, we present WATWAOS, a framework for worst-case-aware tailoring and whole-system analysis of energyconstrained real-time systems. WatwaOS acts as both an analysis/tailoring framework and a (generated) real-time operating system. The approach exploits knowledge acquired during wholesystem analysis and applies worst-case-aware tailoring of the system for its runtime. WatwaOS has an awareness of the application's requirements (i.e., deadlines, peripheral devices) and the underlying SoC's energy-saving features. To achieve the tailoring, WATWAOS introduces a concept of hierarchical abstractions, which offer fine-grained power-management decisions. These abstractions are designed to enable merging of their states without loss of accuracy. Static analysis based on these abstractions yields worst-case-optimal (i.e., provably energy minimal) solutions with regard to given deadlines. To tackle the enormous search space of our bilevel problem, WatwaOS employs several concepts to exploit advanced features of mathematical optimizing tools. The evaluations of WATWAOS validate our claim of finding worst-case-optimal solutions within acceptable analysis times.
Deep neural network (DNN) models are increasingly deployed in real-time, safety-critical systems such as autonomous vehicles, driving the need for specialized AI accelerators. However, most existing accelerators support only non-preemptive execution or limited preemptive scheduling at the coarse granularity of DNN layers. This restriction leads to frequent priority inversion due to the scarcity of preemption points, resulting in unpredictable execution behavior and, ultimately, system failure. To address these limitations and improve the real-time performance of AI accelerators, we propose DERCA, a novel accelerator architecture that supports fine-grained, intra-layer flexible preemptive scheduling with cycle-level determinism. DERCA incorporates an on-chip Earliest Deadline First (EDF) scheduler to reduce both scheduling latency and variance, along with a customized dataflow design that enables intralayer preemption points (PPs) while minimizing the overhead associated with preemption. Leveraging the limited preemptive task model, we perform a comprehensive predictability analysis of DERCA, enabling formal schedulability analysis and optimized placement of preemption points within the constraints of limited preemptive scheduling. We implement DERCA on the AMD ACAP VCK190 reconfigurable platform. Experimental results show that DERCA outperforms state-of-the-art designs using non-preemptive and layer-wise preemptive dataflows, with less than 5 % overhead in worst-case execution time (WCET) and only 6% additional resource utilization. DERCA is open-sourced on GitHub: https://github.com/arc-research-lab/DERCA
