As spin-orbit-torque magnetic random-access memory (SOT-MRAM) is gathering great interest as the next-generation low-power and high-speed on-chip cache memory applications, it is critical to analyze the magnetic tunnel junction (MTJ) properties needed to achieve sub-ns, and ~fJ write operation when integrated with CMOS access transistors. In this paper, a 2T-1MTJ cell-level modeling framework for in-plane type Y SOT-MRAM suggests that high spin Hall conductivity and moderate SOT material sheet resistance are preferred. We benchmark write energy and speed performances of type Y SOT cells based on various SOT materials experimentally reported in the literature, including heavy metals, topological insulators and semimetals. We then carry out detailed benchmarking of SOT material Pt, β-W, and BixSe (1-x) with different thickness and resistivity. We further discuss how our 2T-1MTJ model can be expanded to analyze other variations of SOT-MRAM, including perpendicular (type Z) and type X SOT-MRAM, two-terminal SOT-MRAM, as well as spin-transfer-torque (STT) and voltage-controlled magnetic anisotropy (VCMA)-assisted SOT-MRAM. This work will provide essential guidelines for SOT-MRAM materials, devices, and circuits research in the future.
This work presents a detailed RF characterization of 28 FDSOI nMOSFETs at cryogenic temperatures down to 4.2 K. Two main RF Figures of Merit (FoMs), i.e. current gain cutoff frequency (f(T)) and maximum oscillation frequency (f(max)), as well as parasitic elements of the small-signal equivalent circuit are extracted from the measured S-parameters. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28 FDSOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2 K and clarifies the origin and limitations of the performance.
This paper reports a 28GHz broadband single-pole double-throw (SPDT) travelling wave switch designed in a 22nm fully-depleted silicon-on-insulator (FD-SOI) technology. The 28GHz SPDT TRx switch covers the n257 and n258 bands of 5G systems. Measurements show compatible switch performance compared to similar millimeter-wave switches of various topologies in HEMT and bulk CMOS technologies. The SPDT switches feature full-chip 9KV ESD protection confirmed by measurement. It reveals that ESD-induced parasitic effects may have substantial impacts on mm-wave broadband switches, which hence requires careful ESD-RFIC co-design for 5G RF ICs in above-6GHz bands.
We demonstrate a pathfinding architecture for record CPU performance with clock speed exceeding 20GHz and adequate control of the self-heating and Dark-silicon at these extreme frequencies. The approach relies on the use of double-sided fully-depleted-SOI (DS-FD-SOI) CMOS as key building-blocks in a fully monolithic high-rise 3-Dimentional (3D) CPU. The monolithic 3D architecture embraces a methodic "system-on-top-of-system" approach that effectively suppresses RC-delays by eliminating all global and semi-global on-chip interconnects. The DS-FD-SOI CMOS eliminates the need for Through-Silicon-Vias (TSVs) and enables shorter less resistive vertical interconnections while its secondary Gate contributes further to reducing RC-delays and it also trims the Standby power by up to 4 orders of magnitude. Preliminary simulations on this novel monolithic 3D architecture demonstrates clock-speed up to 20GHz with dynamic losses that are order(s) of magnitude lower than those in today's conventional 2D CPUs that use standard FD-SOI CMOS when these are clocked at 5GHz and interconnected to one another through long global and semi-global interconnects.
In this paper, we study the implementation of a SiOx ReRAM an artificial spiking neuron network (SNN) as a memristive synapse. The analog switching SiOx based resistive random access memory (ReRAM) uses room temperature process and switches at sub 1.2V, suitable for BEOL integration. We analyze the neuron circuit speed impact from ReRAM switching, supply voltage and power consumption. With an single industry I/O voltage of +1.8V besides necessary negative supply for bipolar signal generation, and by co-optimizing the neuron circuit in the region of μs, the operating speed can be 3 orders faster than existing reported SNN circuit. In addition, we show that the ReRAM switching time poses the speed bottleneck for the SNN circuit. In order to further enhance the SNN operating speed, improvement to the ReRAM switching time is needed, or the need to increase the voltage supply but at the expense of power consumption.
This paper presents the analysis of through silicon via (TSV) with embedded capacitor for impedance tuning to improve the power integrity (PI) performance of Application-Specific Integrated Circuit - High Bandwidth Memory (ASIC-HBM) system. The crosstalk due to TSV with embedded capacitor (TSV-Cap) to signal integrity (SI) performance is evaluated by analyzing its frequency response up to 100 GHz and its eye diagram. Using this TSV-CAP, the power distribution network (PDN) impedance is kept below 50 mΩ up to 5 GHz while achieving data rate of 5 Gbps.
This paper outlines different design options and most suitable memory devices for implementing dense vector-by-matrix multiplication operation, the key operation in neuromorphic computing. The considered approaches are evaluated by modeling system-level performance of 55-nm 4-bit mixed-signal neuromorphic inference processor running common deep learning feedforward and recurrent neural network models.
One of the major mechanisms of tunnel transistor operation is `energy filtering', which involves current switching by alignment and misalignment of energy levels in the channel of the transistor. Due to the influence of the contacts, the channel energy levels are never perfectly sharp, but have some broadening. The conventional Lorentzian lineshape leads to unacceptably slow algebraic sub-threshold current fall off. In this paper, we argue that the contacts to the tunnel transistor need to be narrowband, heavy-effective mass wires to achieve sharper-than-Lorentzian current switching.
Response of a metal\ferroelectric Hf0.5Zr0.5O2\metal capacitor to an arbitrary excitation is investigated by polarization reversal curves and switching speed characterization. Results are explained in a steady-state Preisach as well as a modified transient NLS model framework. Applicability and limitations of each model are discussed. Switching speed measurements are found to be sensitive to parasitics. Separation of the intrinsic behavior from parasitics indicates the upper bound of the characteristic time constant of polarization switching speed is around 80ns in our sample.
Nanowire (NW) junctionless accumulation Mode (JAM) FETs were proposed to improve the ON-state current as compared to the conventional junctionless FETs. However, NWJAMFETs suffer from an enhanced detrimental lateral-band-to-band tunneling (L-BTBT) which restricts their scaling to sub-10 nm regime. Therefore, we investigate the scalability of NW JAMFETs using an intrinsic pocket in the extension regions. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket substantially reduces the L-BTBT induced OFF-state current by around 2 orders and 4 orders of magnitude for a gate length of 20 nm and 7 nm, respectively, leading to a significant ON-state to OFF-state current ratio (ION/IOFF) of 106 and 105, respectively and a small DIBL of 12mV/V and subthreshold swing (SS) of 62.2mV/dec for 20 nm gate length device. The NW JAMFET with intrinsic pocket (Pi-NW JAMFET) exhibits superior short channel characteristics due to the reduced electrostatic source/channel-to-drain coupling and a diminished parasitic BJT action in the sub-10 nm regime extending the roadmap for the device scaling. The proposed Pi-NW JAMFETs show superior performance even at a scaled contacted poly pitch (CPP) of 52 nm with IOFF~28pA/um for a gate length of 7 nm. The excellent OFF-state characteristics of Pi-NW JAMFET makes them a lucrative FET architecture for realizing sub-10 nm channel lengths for low power and low leakage applications.
Concerning the innovations in architecture of tunnel-field effect transistor (TFET), the potential to achieve higher on-current increases. In respect thereof, the focus of this paper is on an optimized TFET with higher current flowing through its channel and simulating its static and dynamic behavior using a compact model. The scalability of the model allows to estimate the impact of an on-current improvement on the intrinsic speed and switching energy of TFET inverters through scaling their channel length and supply voltage.
A novel CMOS-enabled heterogeneous integration and packaging technology based on multi-dimensional (MD) integration of thin-film components to combine between the best of SoC IC integration and best of SiP package integration is demonstrated. As a proof-of-concept, we demonstrate a prototype of a cubic MD-IC (4D system) that includes multi-functional sensors, antenna, microcontroller, light-emitting-diode (LED), a micro-lithium-ion battery and a solar cell. Devices are fabricated on both sides of each substrate (Si, Ge and GaSb) and are interconnected using through-silicon-vias (TSVs) and side interlocks. PDMS encapsulation shows improved mechanical performance. The resulting system is a complete, multi-functional, lightweight, high-performance and compact packaged system. The MD-IC package passed preliminary component-level and system-level reliability tests. Finally, the MD-IC provides an enhanced yield and cost of the system due to the capability to fabricate and test smaller dies separately before integrating them into a complete package.
Josephson junctions, cryogenic CMOS, and adiabatic circuits were proposed as computing options decades ago, but never got traction due to competition from room-temperature CMOS. However, quantum computer control electronics naturally requires cryogenic temperatures, making a deeper investigation of these technologies timely. We argue that a technology hybrid and new system design principles are needed, which we illustrate with adiabatic cryo-CMOS circuits playing an unanticipated but very important role. Transistor redesign will lead to even further improvement beyond what's illustrated in this paper, but more research will be needed to know how much.
In this work, using a calibrated 2D TCAD simulation study, we propose and investigate a vertical dual source tri-line-gate (TLG) Tunnel Field-Effect Transistor (TFET) structure with U-shaped n+ pockets. The dual source configuration with U-shaped pockets is sandwiched between three parallel overlapping source-channel vertical line gates. Such a combination minimizes the drain induced barrier thinning effect existing in the conventional L-shaped pocket architecture along with an ON current boosting of ~49% at V DS =V GS =0.7V. The resultant I ON /I OFF ratio is improved by approximately three orders from ~2×10 2 to 1.48×10 5 with a steep subthreshold swing of ~40mV/dec.
A detailed statistical characterization of gate-induced drain leakage variability in FDSOI devices is carried out. An analytical model is developed for the drain current variability, covering the on-state and off-state MOSFET operation regions.
A Micro LED (μLEDs) display, a heterogeneous system, is one that integrates inorganic μLEDs and IGZO thin film transistors made on different substrates with different process flows. Millions of μLEDs are transferred from source wafers and integrated on TFT backplanes to make a display. To guarantee zero defect density, a fault tolerant design (e.g. redundancy) may be adopted. Here, we estimate the required redundancy level for a given display resolution and yields for the μLED source wafers and the transfer process of μLEDs to the backplane. This is done using a novel yield statistical model. The results may be used to assess the capital requirements and the risk involved in making such heterogeneous systems in high volume manufacturing.
We report the effect of the substrate bias (Vsub) and the positive charge (Qox) in the buried oxide (BOX) on P-channel / N-channel super steep subthreshold slope (SS) “PN Body-Tied (PNBT) SOI-FET”. The Qox in the BOX was evaluated with the specific test device. Removing the effect of the Qox and realizing the super steep SS, the necessity of Vsub, especially on P-channel, was systematically confirmed with measurements and simulations. It was founded out that the positive feedback by PNBT contributes to making the barrier height for reducing the leakage current and realizing the super steep SS, although the difference of the static barrier height is small only with Vsub and the Qox. We also propose modification on PNBT structure for realizing CMOS without Vsub bias.
22FDX®, the most advanced FD-SOI technology in volume production, is enabling highly integrated SoCs across IoT, cellular IoT, 5G, and automotive applications. This paper surveys the latest publications on this planar technology by academic and industry research groups. Insights are provided on how its ultra-low voltage, ultra-low leakage, superior mmWave, and robust embedded magneto-resistive RAM (MRAM) features make it the technology of choice for aforementioned applications.
In this paper, a Silicon On Thin Buried-oxide (SOTB) implementation of a 32-point Discrete Cosine Transform (DCT) is presented. The architecture is based on the fixed-rotation adaptive COordinate Rotation DIgital Computer (CORDIC) algorithm.
A 64x1 fuse memory with 0.4V/1uA read at 200kHz and 25°C on 22nm FD-SOI for battery-less RFID is presented. The fuses are programmed below a break point, so that the fuse can be programmed at 0.9V to enable low voltage read. Read current is very low by using a time-based sensing: comparing the capacitor discharge rates through fuse and reference resistors for data 0 or 1.
