This study experimentally investigates the electrical characteristics of seven-level stacked nanosheet SOI nMOSFETs for high-temperature applications. The experimental findings reveal a significant advantage of this architecture, demonstrating a reduced threshold voltage variation with temperature compared to both two-level stacked nanosheet transistors and state-of-the-art Fully-Depleted SOI MOSFETs. Furthermore, analysis of the normalized transconductance per total width indicates that the enhancement in carrier mobility, typically observed for wider nanosheets relative to narrower ones, tends to saturate for wider devices and to reduce as the operating temperature increases. Also, the normalized transconductance per channel length indicates a reduction of mobility for short-channel devices.

This work presents an experimental assessment of self-heating in SOI nanowire MOSFETs in ambient temperatures ranging from 300 K down to 4.2 K using the gate resistance thermometry technique. The temperature increase in the channel region is extracted, and the differential thermal resistance is obtained and plotted as a function of the device temperature. Despite the lower power dissipated by a single nanowire, the operation temperature decrease causes the temperature rise in the channel to increase from around 6 K at room temperature up to 53 K in the cryogenic range. The thermal resistance is considerably lower in nanowires than in widechannel devices, although both types of transistors present an abrupt increase in the differential thermal resistance at extremely low device temperatures.

Due to the miniaturization of transistors, which has scaled down the channel to nanometric dimensions, the influence of parasitic elements such as series resistance has become increasingly critical to device performance. This study presents an experimental investigation of series resistance in a seven-level stacked nanosheet SOI nMOSFET. The impact of fin width, channel length, number of parallel fins, and high temperature on series resistance was analyzed. The results show that the increase in the number of parallel fins demonstrated to lower the series resistance, proportionally to the rise in conductive paths. Furthermore, narrower devices exhibit significantly higher series resistance and larger temperature sensitivity. Although the series resistance has been shown to decrease with channel length reduction, its variation with temperature has been shown to increase in shorter transistors.

This work analyzes the threshold voltage $(\mathbf{V}_{\mathbf{T}})$ variability of IM SOI nanowire (NW) transistors at high temperatures using numerical simulations. The impact of different sources of variability on variation in $V_{T}$ is investigated. Experimental data at 300K reported in the literature were used to calibrate the simulations. Three-dimensional TCAD simulations based on the statistical Impedance Field Method (sIFM) were employed to assess variability. The results indicate that line edge roughness (LER) becomes the dominant source of $\mathbf{V}_{\mathbf{T}}$ variability as temperature increases, while the influence of other variability sources tends to decrease. The observed reduction in total $\mathbf{V}_{\mathbf{T}}$ variability with increasing temperature is in agreement with results reported in the literature.

In this study, an experimental assessment of transport parameters in 7-level stacked nanosheet GAA nMOSFETs is conducted, employing the Y-Function methodology to extract carrier mobility. Specifically, the contribution of horizontal and vertical conduction planes to mobility and degradation factors is investigated for transistors with varying channel lengths and nanosheet widths. The findings reveal that while overall low-field mobility demonstrates weak dependency on nanosheet width, it suffers some reduction in short-channel transistors. Furthermore, the mobility degradation was analyzed, and the results indicate that overall mobility degradation coefficients depend on the nanosheet width, as the balance between horizontal and vertical contributions varies. Notably, while the linear degradation factor dominates the mobility degradation at horizontal planes, vertical planes exhibit a dominant quadratic degradation factor. This suggests larger surface roughness scattering at sidewalls compared to horizontal planes.

Experimental results of analog parameters of nMOSFETs fabricated in a 180 nm commercial CMOS technology, with different channel lengths, operating at temperatures ranging from 300 K down to 93 K, are presented and discussed in this paper. The transconductance-to-current ($\mathrm{g}_{\mathrm{m}}/\mathrm{I}_{\text{DS}}$) ratio, Early voltage ($\mathrm{V}_{\text{EA}}$), and intrinsic voltage gain (Av) were analyzed.

This work presents an experimental evaluation of the influence of the extraction method on the analysis of threshold voltage variability in nanosheet transistors, using seven drain current-based methods. SOI The experimental results of nanosheet transistors with different fin widths and channel lengths show that the choice of the extraction method might change not only the threshold voltage mean value but also its relative deviation.

This work presents an analysis of capacitances in Graded-Channel (GC) SOI MOSFETs using numerical simulations, validated through the comparison to experimental data. The influence of transistors channel length, length of the lightly doped region, and technology parameters downscaling have been investigated through two-dimensional numerical simulations.

This paper evaluates the electrical characteristics of Inversion-mode (IM) and Junctionless (JNT) SOI nanowire MOSFETs across a temperature spectrum from 300K to 82K. The study examines devices with varying fin widths, utilizing experimental data to analyze crucial electrical metrics, including threshold voltage, inverse subthreshold slope, and carrier mobility throughout the temperature range. The investigation also explores how these parameters are influenced by channel length and fin width.

This study assesses the analog parameters of 7-level stacked SOI nanosheet transistors. The impact of nanosheet width, channel length, and bias condition is thoroughly examined through the analysis of experimental data. Key parameters, including transconductance, output conductance, and intrinsic voltage gain, are used as figures of merit for this investigation. A comparative analysis with data available in the literature reveals that the intrinsic voltage gain exhibits less sensitivity to nanosheet width when compared to single-level and 2-level stacked nanosheets.

This paper investigates the separation of the drain current components in top-bottom and sidewall currents, and the extraction of their respective low-field mobility in two-level stacked nanowire nMOSFETs. The study presents a detailed analysis of carrier transport in different crystallographic planes, emphasizing the anisotropy in mobility due to variations in sidewall roughness induced by the etching process. Devices with variable fin widths (WFIN) were measured. The effective mobility and the mobility degradation factors were extracted using the Y -function method. This study provides insights into the optimization of process and device modeling for stacked nanowire MOSFETs.

This work presents an analytical model for the drain and gate currents of silicon nanowire and nanosheet MOS transistors valid in all operating regions in the temperature range from 300 to 500 K. Analytical models for the tunneling components as well as for the reversely biased drain-to-channel PN junction are presented. Also, the models accounting for the necessary modifications in the silicon physical quantities for high-temperature operation, such as the maximum carrier mobility, the bandgap, and the intrinsic carrier concentration, are presented. The proposed model uses a single set of parameters, extracted at room temperature, to describe the high-temperature operation of silicon nanowire MOSFETs. The model is validated with comparisons between modeled and experimental results for devices with different fin widths and operating temperatures, with good agreement.

This article aims to present experimental results of nMOSFETs from a 180 nm commercial CMOS technology, with different channel lengths, operating at temperatures ranging from 80 K to 300 K. The source-drain resistance $(\mathbf{R}_{\mathbf{SD}})$ , threshold voltage $(\mathbf{V}_{\mathbf{TH}})$ , subthreshold slope (SS), low-field mobility $(\boldsymbol{\mu}_{\mathbf{0}})$ , and the linear $(\boldsymbol{\theta}_{\mathbf{1}})$ and quadratic $(\boldsymbol{\theta}_{\mathbf{2}})$ mobility degradation factors were extracted. The extraction of $\mathbf{R}_{\mathbf{SD}}$ yielded an average value of $\mathbf{61.90} \pm \mathbf{3.83}\ \mathbf{\Omega}$ all devices and temperatures. Comparing all the devices, as the temperature decreased, $\mathbf{V}_{\mathbf{TH}}$ showed an increase in its value between 22.3 % and 33.9 %; SS showed a decrease between 59.7 % and 62.1 % of its value; $\boldsymbol{\mu}_{\mathbf{0}}$ increased 162.4 % for the shorter device and 243.2 % for the longer device; $\boldsymbol{\theta}_{\mathbf{1}}$ varied less for longer devices; and $\boldsymbol{\theta}_{\mathbf{2}}$ showed more variations in its values, being less intense in shorter devices. Analyzing the channel shortening, the rate of change $\mathbf{dV}_{\mathbf{TH}}/\mathbf{dT}$ showed, in magnitude, a decrease from 0.696 mV/K to 0.561 mV/K, the rate of change dSS/dT showed an increase from $\mathbf{0.197}\ \mathbf{mV} /(\mathbf{dec} \cdot \mathbf{~K})$ to $\mathbf{0.223}\ \mathbf{mV}/(\mathbf{dec}\cdot \mathbf{K})$ , and the ZTC was from 0.67 V to 0.77 V.

This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling.

In this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.

This work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.

The threshold voltage is a key parameter for MOSFET modeling and can be extracted by several methods reported in the literature. However, for a given device, different methods result in different extracted values, which may cause doubt about its exact value. This paper compares the threshold voltage in SOI nanowire transistors extracted through eight different methods based on drain current measurements. Devices with different widths and lengths measured at different temperatures are analyzed. Results show that different methods can result in different values with distinct variation rates with dimensions and temperature change.

Nanowire transistors constitute an alternative for the continuous downscaling of MOSFETs. These devices present a trigate architecture featuring the fin width (WFIN) and height (HFIN) with similar dimensions, in the order of tenths of nanometers [1], which improves the gate control on the channel charges, reducing short-channel effects (SCE) and improves electrical properties in both digital and analog applications [1]. Junctionless nanowire transistors (JL) are easier to fabricate than inversion-mode MOSFETs [2]. They also are less vulnerable to the occurrence of SCE, which is one of the main concerns when downscaling the MOS transistor [3, 4]. Unlike inversion mode (IM) transistors, the junctionless device is made with a heavily doped silicon layer with the same doping type from source to drain [2, 5]. To lower the series resistance, the source and drain receive an additional doping step to increase their concentration. Although JL transistors are a good alternative for the continuous downscaling of MOS transistors, they still have their basic operation like any other transistor MOSFET. Therefore, it is not completely immune from SCE, such as Drain-Induced Barrier Lowering (DIBL) effect. In this work, a comparison between the DIBL effect in junctionless and inversion-mode nanowire transistors is performed. Experimental results at room and high temperatures are presented for devices with different channel widths. The JL and IM nanowire transistors used in this work were fabricated at CEA-Leti, as described in reference [6]. Devices with 10 parallel channels and channel length (L) of 40 nm and 100 nm were measured, fin width (WFIN) of 12 nm, 17 nm, 22 nm, and 42 nm. Two different values of drain voltage (VD) were applied for all devices, VD1 = 40 mV and VD2 = 800 mV. Finally, the DIBL has been calculated as DIBL=|VT2 – VT1| /(VD2 – VD1). The threshold voltage in both VD has been extracted as described in ref. [7]. The analysis for DIBL as a function of fin width is shown in Figure 1(A). For devices with L=100nm, no SCE has been observed and all devices present Subthreshold Slope (SS) close to the theoretical limit. Also, for WFIN up to 22 nm, DIBL is the same both for IM and JL nanowires. When downscaling the length to 40 nm, despite of DIBL increase for all devices, no degradation on SS is seen for JL, whereas IM devices exhibit SS>82mV/dec. Considering reasonable characteristics, i.e., DIBL=100mV/V and S=80 mV/dec [8], except from WFIN=42nm, all JL devices meet these requirements, whereas no IM nanowire with L=40 nm could be used. Even if maximum allowable DIBL were increased to 120mV/V, only the narrowest IM with L=40nm would be acceptable. Aiming to verify the influence of the temperature on the DIBL, Figure 1(B) shows the variation of DIBL in relation to room temperature for IM and JL nanowires with L=100nm and WFIN=12nm, which have similar DIBL at 300K. One can see that DIBL variation with temperature in the IM device is larger than in JL. While the IM transistor presented a DIBL variation of 0.15(mV/V)/K, for the JL one, it is 0.11(mV/V)/K. These results indicate that apart from the good immunity to SCE, JL nanowires are less susceptible to DIBL variation with temperature. Acknowledgements The authors thank financial support from CAPES, CNPq and FAPESP. References [1] T. A. Oproglidis, T. A. Karatsori, S. Barraud, G. Ghibaudo and C. A. Dimitriadis, Effect of Temperature on the Performance of Triple-Gate Junctionless Transistors, in IEEE Transactions on Electron Devices, vol.65, no.8, pp.3562-3566, 2018. [2] J.-P. Colinge et al, Junctionless Nanowire Transistor (JNT): Properties and design guidelines, Solid-State Electronics, Volumes 65–66, 2011, Pages 33-37. [3] J.-P. Colinge, Junctionless transistors, 2012 IEEE International Meeting for Future of Electron Devices, Kansai, 2012, pp. 1-2. [4] M. Ehteshamuddin, Sajad A. Loan and M. Rafat, Excellent DIBL Immunity in Junctionless Transistor on a High -k Buried, 2017 14th IEEE India Council International Conference (INDICON). [5] T. A. Ribeiro, M. A. Pavanello, Analysis of the electrical parameters of SOI junctionless nanowire transistors at high temperatures, Journal of the Electron Devices Society, April 2021. [6] D. Bosch et al., All-Operation-Regime Characterization and Modeling of Drain Current Variability in Junctionless and Inversion-Mode FDSOI Transistors, 2020 IEEE Symposium on VLSI Technology, 2020, pp. 1-2. [7] M. De Souza et al, Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors, ESSDERC 2021, pp. 223-226, 2021. [8] J.-W. Yang and J. G. Fossum, On the feasibility of nanoscale triple-gate CMOS transistors, in IEEE Transactions on Electron Devices, vol. 52, no. 6, pp. 1159-1164, June 2005. Figure 1

This work presents the electrical characterization of Ω-gate SOI nanowire MOSFETs in the temperature range from 82 K to 330 K. Devices with different fin widths and channel lengths are compared. The comparison is performed using experimental data looking for some of the fundamental electrical parameters such as threshold voltage, inverse subthreshold slope, and carrier mobility over the temperature. For short-channel devices with L=40 nm an analysis of the mobility degradation coefficients over the temperature is performed.

This work compares the Drain-Induced Barrier Lowering (DIBL) effect in SOI nanowire transistors. The fin width, length, and temperature influence are experimentally evaluated for junctionless (JL) and inversion mode (IM) nanowire transistors. The results show that DIBL degradation with length reduction is more pronounced in IM nanowires. Although the DIBL might be higher on JL nanowires, its temperature variation has been reduced compared to IM devices.