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    International Conference on IC Design & Technology

    International Conference on IC Design & Technology

    Conference

    年发文量

    研究主题

    论文(598)

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    1Enhanced Ferroelectricity in Hf 0.5 Zr .5 O 2 Thin Films by NLA at Intermediate Laser Energy Density.
    David Lehninger, Tianren Zhang,Peter Reinig, Justine Barbot, Mathieu Opprecht, Sébastien Kerdilès,Laurent Grenouillet,Konrad Seidel,Maximilian Lederer
    2025
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    2A 3-V, 72-Μw and 0.042-Mm 2 Active-Area Dynamic Comparator in Flexible TFT Technology.
    Muhammad Zahid Naveed,Marco Privitera,Alfio Dario Grasso,Gianluca Giustolisi

    This paper presents a dynamic comparator designed and simulated in a 0.6-mu m indium-gallium-zinc oxide (IGZO) thin-film transistor (TFT) process on a flexible substrate. The proposed circuit operates from a 3-V supply, consumes only 72 mu W of power, and occupies a compact area of 0.042 mm(2). Building upon a double-tailed comparator topology adapted to an all-nTFT process, the design incorporates a fixed-bias preamplifier to enhance offset tolerance and mitigate kickback noise. Post-layout simulations confirm robust performance at clock frequencies up to 200 kHz, with an offset voltage below 10 mV across various process corners. These results highlight the feasibility of implementing high-performance mixed-signal circuits on flexible substrates, enabling applications in large-area, low-cost systems such as sensor interfaces and data converters.

    2025
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    3A 5 V Pp 10-Bit 100ms/s Current-Steering DAC As MZM Drivers of PNN Systems.
    L. S. S. Pavan Kumar Chodisetti, Chen-Wei Yen, Pradyumna Vellanki, Yung Hung,Chua-Chin Wang
    2025
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    4A 5.06ppm/°c, -81.5Db-psrr, 4.85µa Bandgap Reference with Curvature Correction in 55nm CMOS.
    Francesco Spreafico,Luca Sant,Richard Gaggl,Andrea Baschirotto
    2025
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    5Push-Pull Current Mode Filters in 65 Nm CMOS Technology
    Stefano D'Amico, Alessio Luongo, Christophe Genevois

    Current mode filters have gained momentum due their better fit to low supply voltage. With respect to the voltage mode counterpart, current mode filters reach a lower input referred noise as the bias current is lowered, enabling significative power saving. Indeed, the noise current is proportional to the bias current. However, the bias current reduction makes arising linearity issue, as the amount of signal current that can be processed is, generally, proportional to the bias current. This is why a push pull current mode filter able to overcome the limitation imposed by the bias current to maximum handleable signal current is proposed. Designed in a 65 nm CMOS technology, the push-pull current mode filter achieves a 3 times higher 1 dB compression point with respect to the simple current mode version. The cost is paid in terms of area, which may increase by up to 50% compared to the simple version, while power consumption remains unaffected.

    2025
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    高被引作者

    作者引用发文
    Michael Orshansky1742
    Anirudh Devgan1671
    M Mani1671
    Maud Vinet1007
    Chua-Chin Wang9319
    Chun Zhao889
    Alexander Demkov842
    Youri Popoff831
    Morgan Trassin831
    Chiara Marchiori831

    高产作者

    作者引用发文
    Chua-Chin Wang9319
    Wen Liu6218
    Andrea Baschirotto4217
    De Matteis, M.4114
    Stefano D'Amico4414
    Ivona Mitrovic1811
    Yang Li1011
    Cezhou Zhao1810
    Huiqing Wen2710
    Chun Zhao889

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