A new TDDB lifetime model is proposed to predict lifetime for AC inverter-like stress in FinFET device. The AC lifetime is governing by four mechanisms, including voltage switching, electron detrapping, HCI and hole injection. Among them, voltage switching and electron detrapping improve TDDB lifetime; while HCI and hole injection degrade the lifetime.
Localized Thermal Effect (LTE, i.e. self-heating) is one of the greatest reliability concerns of FinFET technologies. This paper introduced some new reliability design methodologies for aging and electromigration to address the LTE effects at circuit level. An industry level PLL circuit designed on a leading foundry's sub-16nm FinFET process was applied with the new methodologies to analyze the LTE impacts on the circuit reliability. The results not only showed very different behaviors and impacts of temperature accelerated degradations on circuit performance and functionality with and without comprehending LTE effects, but also demonstrated the effectiveness of the new LTE-aware design for reliability methodologies developed and deployed at Hisilicon.
In this paper, fundamental reliability findings in 14nm bulk FinFET technology, are systematically investigated. From device and Ring Oscillator stress to product-level HTOL results, we show that BTI on (110) Fin can be improved significantly with optimized process. In addition, BTI variability with small Fins does not pose any fundamental risk and we'll show 1000hrs of HTOL data on 128Mb SRAM. Fin Self-heating effect (SHE) was characterized for both logic and I/O devices and verified through simulations and thermal imaging for product design and verifications. Overall, robust 14nm FinFET reliability has been demonstrated on the product level through full process optimizations and stress validations.
This paper describes the critical importance of interfacial strength between copper lines and cap layer for catastrophic failure due to chip-package interaction (CPI). Recently, copper interconnects and insulating layers are stacked alternately in semiconductor devices. Especially, copper/low-k structures are widely selected. However, the low-k materials have weak mechanical properties, which sometimes induces reliability issues, especially, chip package interactions. In our previous works, the interfacial strength of Cu/Cap has been successfully measured on the sub-micron scale. In this paper, based on the measured results, we try to simulate the initiation and propagation of failure in interconnect structures and discuss the scenario for catastrophic failure under CPI.
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip were evaluated. The retention characteristics of memory cells were degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness in the case with under-fill, meanwhile, the retention characteristics were relatively not so degraded until to 30-μm thickness, but suddenly degraded below 20-μm thickness in the case without under-fill. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300oC annealing. Meanwhile, the retention characteristics in the thinned DRAM chip which was DP-treated did not degrade regardless of the well structure. The retention characteristics of some memory cell arrays with Cu TSV arrays began to degrade after annealing at 300oC for 30min. As the annealing temperature increase higher than 400oC, Cu atoms more spread out into larger area in the DRAM chip via poor barrier layers.
We developed nearly-independent electrical "signature parameters" for surface pitting, hot electron damage, and electron trapping in GaN HEMT RF power devices. We then used the surface pitting signature parameter to find the rate of this degradation mechanism, without influence from the other mechanisms, occurring concurrently. This is important so the extracted thermal activation energy for this common mechanism is correct, allowing accurate extrapolations to operating temperatures. We then utilized a new technique (described in detail elsewhere) to scale these measurements in DC lifetests, to normal RF operating conditions.
The reliability of 600 V GaN power switches, fabricated in a silicon CMOS foundry, has been demonstrated. JEDEC qualification of cascode packages and the long term reliability of GaN power switches has been estimated for the first and shown to be greater than a million hours. Excellent switched/dynamic on-resistance up to 1000 V and breakdown voltage over 1500 V indicate the suitability of these devices for switching up to 480 V. Detailed data of high temperature reverse bias (HTRB) test is shown. High temperature DC stress test and high voltage off-state stress tests also corroborate the high reliability of these devices. This suite of initial, JEDEC & accelerated stress tests show that GaN-on-silicon power switches are ready for many commercial and industrial applications, would significantly reduce switching losses and system size and will impact all areas of electricity conversion, ranging from tablet chargers to photovoltaic inverters and electric vehicles.
Positive Bias Temperature Instability (PBTI) and Hot Carrier Injection (HCI) characterizations on InGaAs-On Insulator (OI) back gate nMOSFETs are presented and the degradation mechanism is discussed. Devices with two ultra-thin body thickness (15 nm and 8 nm) but same buried oxide (BOX) (15 nm) are investigated from a reliability perspective. Independent of the body thickness, the PBTI stress shows stronger impact on device performance than the HCI stress. Although the thinner body transistor exhibits a lower “off” current, it subjects to more severe degradations under both PBTI and HCI stresses. Pulsed HCI experiments confirmed that the self-heating effect (SHE) compounds the reliability challenge in ultra-thin body InGaAs-OI nMOSFETs. Additionally, it is also found that the different evolutions of the threshold voltage and the saturation current of the UTB InGaAs-OI nMOSFETs may be due to the slow border traps in the oxide.
Embedded non-volatile memories (NVM) use extensively designed-in error correction coding solutions to assure a low chip failure rate (CFR) even with unavoidable single bit failures. The monitoring data of the bit failure rate (BFR) can be used together with a CpK approach to demonstrate the production capability with low CFRs at least for the qualification.
The mechanical properties of silicon substrate begin to deteriorate with the wafer thinning process particularly when thicknesses approach 50um or below. Key mechanical indexes such as Young's modulus, hardness and fracture toughness are characterized by nanoindentation method to study the impact of thinning wafers on critical electrical parameters. It has been published that the lattice structure of Si substrate becomes highly distorted for wafer thicknesses below 50um. Depending on the magnitude of this distortion in the lattice structure, a reduction in Young's modulus is generally observed. However, we demonstrate a thinning process that shows minimal impact on device reliability.
A methodology is presented for generating the appropriate time-to-failure probability density function (pdf) for any arbitrary degradation-rate time dependence. The methodology presented serves to establish the critically important statistical link between material degradation-rate and device failure-rate. No longer does the reliability engineer need to simply choose between either Weibull or log-normal pdf.
We present both heavy ion and alpha test results for SPARCV8 pipelined-microprocessors fabricated in a space CMOS 65nm platform. Two design implementations, standard and radiation-hardened, are compared at 50/300MHz and 0.8V/1.2V. The dominant failure modes are identified and the failure cross-section is compared with fault injection prediction.
One of technical hurdles in far back-end of line (FBEOL) process is to assure lower solder bump contact resistance (Rc) associated with photosensitive polyimide (PSPI) and under bump metal (UBM) process. Often, higher bump Rc results in low Vcc shift fails in high performance SoC product. With palpable understanding of outgassing behaviors of PSPI and meticulous characterization of degassing phenomena linked to plasma etch with physical vapor deposition (PVD), we successfully achieved <; 10mΩ bump Rc even with a low cost PSPI without an existing PVD refurbishment. From photo process to package reliability, a far back-end process optimization for cost effective bump production will be presented.
In this paper, we present the results of a detailed study done on the correlation between frequency dispersion observed in AC admittance measurements and threshold voltage shifts observed in BTI reliability measurements on III-V MOS devices. We developed a detailed AC admittance model for MOS devices with border traps to study the effect of trap parameters on the AC admittance. We show, with the help of simulations and experiments, a clear correlation between border trap characteristics in AC admittance and BTI behavior. In addition, we propose a simplified and quick method to qualitatively characterize border traps using G/ω as a measure for their density.
This work presents a study of the effect of chip temperature on Photon Emission Microscopy (PEM) images acquired with an extended sensitivity near-infrared camera. A detailed analysis of the detection of thermal radiation, as well as leakage and switching signal components will be presented as a function of the camera spectral tailoring. Time-integrated and Time-Resolved Emission (TRE) measurements collected from a 32 nm SOI testchip are used to show that the leakage component is dependent on temperature, while the switching is not. Moreover, the different SNR optimization based on camera spectral tailoring and chip operating temperature is shown for different types of measurements.
The impact of nitrogen concentration on the negative bias temperature instability (NBTI) effect in p-MOSFETs with SiON gate dielectrics is investigated in this paper. The universal NBTI model considering the interface state generation and hole-trapping/detrapping mechanisms is used for modeling the nitrogen enhanced NBTI degradation. Increased nitrogen concentration increases the interface trap density and reduces the activation energy. Correspondingly, the critical model parameters such as the hole-capture time constant and the interface state generation rate are modified. The universality of NBTI model is verified by comparing with the measurement data under conditions of different nitrogen concentrations. Based on the universal NBTI model, the impact of nitrogen on interface-state generation and hole-trapping mechanisms are investigated respectively. The result shows that interface-state generation is more sensitive to nitrogen concentration variation than hole-trapping mechanism. Therefore, the nitrogen enhance NBTI degradation in the high frequency circuit is not as significant as that under low frequency or DC operation conditions.
A new enhanced displacement-current triggering by adding floating P+ diffusions at each source finger edge for the HV LDNMOSFET is proposed. Unlike the conventional substrate-triggered ESD protection technologies, it is very easy to implement the scheme by the layout without any special circuit and additional component. With a total width of 1600 μm, the HBM/ MM ESD performance improvements from 1.5 kV/ 150 V to 5.5 kV/ 450 V are achieved.
From the experimental measurements, the dominant charge source for a packaged IC chip during a charged-device model (CDM) ESD event is the capacitor between the die-attach plate and the metal bus line, CSUB. By adding a bonding wire between the die-attach plate and the Vss pin, a parallel inductor to the CSUB can be created. The CDM-robustness for the packaged IC chip is significantly improved because of this parallel LC resonance circuit.
In this paper, we use low frequency noise (LFN) measurements to study the resistance drift of the low resistance (SET) and the high resistance (RESET) states Ge-rich based PCM devices. We confirm that the structural relaxation of the amorphous phase, which is at the origin of the drift of the RESET state, also results in an increase of the normalized noise. We then highlight for the first time the decrease of the normalized noise (S I /I 2 ) of the SET states obtained with different programming procedures, which originates from the structural relaxation of the amorphous-like grain boundaries (GB). This demonstrates the major electrostatic influence of the interfacial defects on the LFN of the SET states. The results are successfully interpreted in the framework of recently published models which give account for the drift of the SET and RESET states.
There is a fundamental tradeoff between processor performance and lifetime reliability. High throughput operations increase power and heat dissipations that have adverse impacts on lifetime reliability. On the contrary, lifetime reliability favors low utilization to reduce stresses and avoid failures. A key challenge of understanding this tradeoff is in connecting application characteristics to device-level degradation behaviors. Using a full-system microarchitecture and physics simulation, the performance-reliability tradeoff in a multicore processor is analyzed by introducing a metric, throughput-lifetime product (TLP). A finding reveals that reducing the variance of degradation distribution on the multicore die leads to effectively enhancing processor lifetime with minimal impact on performance. This concept is referred to as dynamic reliability variance management (DRVM). We discuss three possible microarchitectural techniques that perform DRVM and improve the TLP; i) phase-aware thread migration, ii) dynamic voltage scaling, and iii) turbo-mode execution combined with DRVM. The simulation results with selected PARSEC and SPLASH-2 benchmarks show that DRVM techniques improve processor lifetime up to 15% or enhance the throughput-lifetime tradeoff by 12% without adding extra design margins or spare components on the multicore die.
