We have performed real-time soft error rate (SER) measurements on bulk 65 nm static random-access memories (SRAMs) during deuterium–deuterium (D-D) plasma operation at W–tungsten– Environment in Steady-state Tokamak (WEST). The present measurement campaign was characterized by the production of several tens of long pulse discharges (~60 s) and by a total neutron fluence (at the level of the circuits under test) up to ~10 9 n.cm -2 , improving the error statistics by a factor of more than 6 with respect to the first measurements obtained in 2020. Experimental results demonstrate the occurrence of bursts of single-event upsets (SEUs) during the most efficient shots and 12% of multiple cell upset (MCU) events. Time-resolved data also show that MCUs are preferentially detected in the last part of these long pulses, providing further evidence that higher energy neutrons, initiated by deuterium–tritium (D-T) reactions due to triton burn-up in the D-D plasma, may play a role in the production of multiple cell upsets that cannot be attributed in such large proportions to “low energy” neutrons produced in D-D reactions.

Synergy effect of total ionizing dose (TID) on alpha-soft error rate (alpha-SER) in FDSOI 28 nm SRAM has been experimentally characterized using a dedicated setup combining alpha-particle irradiation (241Am solid source) in vacuum chamber and 10 keV X-ray irradiation. Measurements have been performed on a 3 Mbit single-port SRAM cut powered at 1 V. Irradiations up to 125 krad(Si) have been achieved and their impact on the alpha-SER has been characterized from the cumulated number of bitflips as a function of the exposition time to the alphasource. Modelling and simulation have been used to link transistor threshold voltage variations to SRAM cell stability in terms of static noise margin (SNM), critical charge (Qcrit) and finally estimated SER, in good agreement with experimental results.

We conducted a real-time soft-error rate characterization of CMOS bulk 65-nm static random access memories (SRAMs) subjected to fusion neutrons during deuterium–deuterium (D-D) plasma operation at W–tungsten–Environment in Steady-state Tokamak (WEST). The test equipment, installed in the experimental hall at several locations of the tokamak, was irradiated during machine shots by a flux of particles dominated by primary 2.45-MeV neutrons. Real-time neutron metrology, neutron spectrometry, complementary characterization with monoenergetic neutrons, and Monte Carlo numerical simulations at both material and circuit levels have also been performed to analyze the experimental data. Our results suggest that higher energy neutrons, simultaneously produced by deuterium–tritium (D-T) reactions due to triton burn-up in the D-D plasma, play a significant role in the radiation response of SRAMs for which multiple cell upsets are detected and cannot be attributed to D-D neutrons.

TCAD simulations on 28-nm fully depleted silicon on insulator structures are used to analyze the charge collection mechanism leading to parasitic current when an ionizing particle passes through the devices. A description of the components constituting the parasitic current is carried out for several strike locations. The bipolar effect does not arise as the main cause of the parasitic current as usually reported. The impact of the drain-source polarization in the collection mechanism is highlighted. A compact model was made, and a quantitative effect was simulated for the pass-gates in an SRAM cell using a variation of the bitline supply.

Altitude and underground real-time soft error rate (SER) measurements on SRAM circuits have been analyzed in terms of independent multi-Poisson processes describing the occurrence of single events as a function of bit flip multiplicity. Applied for both neutron-induced and alpha particle-induced SERs, this detailed analysis highlights the respective contributions of atmospheric radiation and alpha contamination to multiple cell upset mechanisms. It also offers a simple way to predict by simulation the radiation response of a given technology for any terrestrial position, as illustrated here for bulk 65nm and 40nm SRAMs.

Power estimation of a complex circuit such as a processor is an important but complicated task. The power information is important either for accurate power budgeting at design time or for energy optimization algorithms at run time. However, full simulations are slow and direct analog power monitors are complicated to integrate on-chip. Another approach consists in power estimation by activity as a proxy : it does not rely on the direct measurement of the physical voltage and current quantities; it rather proceeds in estimating the circuit digital activity, and based on known specific ASIC topology and process characteristics, estimate the power consumption. This monitoring is flexible and directly implementable at RTL level. This research note first describes the principle of power estimation by activity proxy and gives a literature overview. Then it details its implementation in a LEON3 processor, taking advantage of its existing L3Stat statistics unit. Quantitative accuracy of the model is presented, showing between 1.5% and 2.1% average error across different testbenches.

This paper reports five years of real-time soft error rate experimentation conducted with the same setup at mountain altitude for three years and then at sea level for two years. More than 7 Gbit of SRAM memories manufactured in CMOS bulk 40 nm technology have been subjected to the natural radiation background. The intensity of the atmospheric neutron flux has been continuously measured on site during these experiments using dedicated neutron monitors. As the result, the neutron and alpha component of the soft error rate (SER) have been very accurately extracted from these measurements, refining the first SER estimations performed in 2012 for this SRAM technology. Data obtained at sea level evidence, for the first time, a possible correlation between the neutron flux changes induced by the daily atmospheric pressure variations and the measured SER. Finally, all of the experimental data are compared with results obtained from accelerated tests and numerical simulation.

We present both heavy ion and alpha test results for SPARCV8 pipelined-microprocessors fabricated in a space CMOS 65nm platform. Two design implementations, standard and radiation-hardened, are compared at 50/300MHz and 0.8V/1.2V. The dominant failure modes are identified and the failure cross-section is compared with fault injection prediction.

This work presents a single-supply SPARC 32b V8 microprocessor designed with Ultra Low Voltage (ULV) adapted standard cells and memories, aiming at low energy operation and stand by power. The microprocessor, equipped with 10 Transistors ULV bitcell 8KB SRAM cache, has been fabricated in Fully Depleted Silicon On Insulator (FDSOI) 28nm technology. A comparative analysis with similar implementations has been provided highlighting the performance gain and power savings that are achieved by our design methodology and implementation technology. Wafer-level tests showed that our ULV adapted microprocessor has an operating range that is functional down to 0.33V and that the ULV able cache can save from 30% to 62% energy.

This paper surveys ten years of experimentation conducted on the Altitude SEE (Single Event Effects) Test European Platform (ASTEP), a permanent mountain laboratory opened in 2005 on the Plateau de Bure (Dévoluy, France) at the altitude of 2552m and primarily dedicated to the characterization of soft errors in electronic circuits subjected to terrestrial cosmic rays. The paper retraces the foundations of the project and gives an extensive overview of the different past, current and future experiments conducted on ASTEP in the fields of SER (soft error rate) real-time testing and natural radiation monitoring and metrology.

This work describes a new computational approach for modeling the radiation-induced transient current and charge collection at circuit-level. Our methodology is based on a random-walk process that takes into account both diffusion and drift of radiation-induced minority carriers in a non-constant electric field both in space and time. The model has been successfully coupled either with an internal routine or with SPICE for circuit solving and feedback on the charge-collection process. It is illustrated here for a junction impacted by an ionizing particle and embedded in a CMOS inverter.

Real-time (life) testing of the soft-error rate (SER) is an experimental reliability technique to determine the soft error sensitivity of a given component, circuit or system from the monitoring of a population of devices subjected to natural radiation and operating under nominal conditions. We present here a survey of real-time testing results accumulated from 2006 at mountain altitude on the Altitude SEE Test European Platform (ASTEP) and underground at the Underground Laboratory of Modane (LSM). Radiation data concern three generations of SRAMs manufactured in CMOS 130, 65 and 40 nm technologies.

Recently (IEEE Trans. Nucl. Sci., Vol. 60, No. 3, pp. 1876-1911, 2013), Reed published an anthology of contributions from different research groups, each developing and/or applying Monte Carlo-based radiation transport tools to simulate a variety of effects that result from energy transferred to a semiconductor material by a single particle event. The Tool suIte for rAdiation Reliability Assessment (TIARA) simulation platform and its development by STMicroelectronics and Aix-Marseille University is described in this paper as a complement to this anthology.

The real-time (or life testing) soft-error rate (SER) measurement is an experimental reliability technique to determine the soft error sensitivity of a given component, circuit or system from the monitoring of a population of devices subjected to natural radiation and operating under nominal conditions. This review gives a survey over recent real-time SER experiments, conducted in altitude and/or underground, and investigating modern CMOS logic technologies, down to the 40 nm technological node. The review also includes our different contributions conducted during the last decade on the ASTEP Platform (Altitude Single Event Effects Test European Platform) and at the LSM facility (Underground Laboratory of Modane) to characterize soft error mechanisms in advanced static (SRAM) memories. Finally, the review discusses the specific advantages and limitations of this approach as well as its comparison with accelerated tests using intense particle beams or sources. (C) 2014 Elsevier Ltd. All rights reserved.

A new computational model for charge transport based on parallelized random-walk drift-diffusion is proposed. This approach models the radiation-induced charge carriers as charge packets in a 3-D structure and the transport modeling are based on simple physical equations without any fitting parameter. This model has been dynamically coupled with a SPICE circuit simulator to take into account temporal variations of the electric fields in the charge collection process. Thus, the circuit electrical response modulates the charge collection efficiency. Three simulation cases have been explored and compared with TCAD simulations or radiation experiments in 65 nm technology to validate the accuracy of the proposed approach. These simulations demonstrate the capability of the proposed model to accurately estimate the soft error rate of complex structures, such as flip-flops over a large range of ionizing particle linear energy transfer. The proposed simulation methodology is also able to take into account charge-sharing phenomenon, and this point is highlighted by a specific investigation on the considered flip-flop.

In this paper, we present the heavy-ion radiation test results for a 7-stage SPARC micro-processor. Special software handlers enabled fine grained classification of the types of crashes. The measured crash cross sections are compared with those predicted by fault injection simulation.

This work reports the combined characterization at mountain altitude (on the ASTEP Platform at 2552 m) and at sea-level of more than ~50 Gbit of 90 nm NOR flash memories subjected to natural radiation (atmospheric neutrons). This wafer-level experiment evidences a limited impact of the terrestrial radiation at ground level on the memory SER evaluated without ECC. Experimental values are compared to estimations obtained from Monte Carlo simulation using the TIARA-G4 code combined with a physical model for charge loss in such floating-gate devices.

Todays' MPSoC applications are requiring a convergence between very high speed and ultra low power. Ultra Wide Voltage Range (UWVR) capability appears as a solution for high energy efficiency with the objective to improve the speed at very low voltage and decrease the power at high speed. Using Fully Depleted Silicon-On-Insulator (FDSOI) devices significantly improves the trade-off between leakage, variability and speed even at low-voltage. A full design framework is presented for UWVR operation using FDSOI Ultra Thin Body and Box technology considering power management, multi-VT enablement, standard cells design and SRAM bitcells. Technology performances are demonstrated on a ARM A9 critical path showing a speed increase from 40% to 200% without added energy cost. In opposite, when performance is not required, FDSOI enables to reduce leakage power up to 10X using Reverse Body Biasing.

This work reports the real-time Soft-Error Rate (SER) characterization of more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and subjected to natural radiation (atmospheric neutrons). This experiment has been conducted since March 2011 at mountain altitude (2552 m of elevation) on the ASTEP Platform. The first experimental results, cumulated over more than 7,500 h of operation, are analyzed in terms of single bit upset, multiple cell upsets, physical bitmap and convergence of the SER. The comparison of the experimental data with Monte Carlo simulations and accelerated tests is finally reported and discussed.