We present the first experimental machine learning (ML)-enabled Process-Technology Co-Optimization (PTCO) framework for optimizing 2D transition metal dichalcogenide (TMD) FET fabrication directly from statistically meaningful experimental data rather than pure simulation data. We first introduce a transition voltage metric, VTrans, to quantify the gate voltage required for off-to-on switching and reveal its direct correlation with subthreshold swing (SS), highlighting an overlooked switching characteristic that governs both off-state and on-state performance. By integrating automated metric extraction, multi-objective recipe ranking, and predictive modeling, our framework uncovers hidden process-performance correlations and predicts the performance of unexplored fabrication recipes from limited experimental data. Experimental validation shows close agreement with ML predictions, thus demonstrating the framework's ability to efficiently guide gate stack optimization through iterative experimental feedback.

Integrating two-dimensional semiconductors, such as MoS2, with dielectric materials remains a central challenge for their use in future logic technologies. While seed layers are typically introduced to promote dielectric nucleation and adhesion, we show that they also critically govern charge transfer doping and, in turn, transistor performance. Back-gated monolayer MoS2 transistors passivated on their top surface with a Ta-seed/HfOx dielectric stack were fabricated and characterized electrically and physically using Raman, photoluminescence, and X-ray photoelectron spectroscopies. Threshold voltage and on-current varied strongly with Ta-seed thickness and deposition conditions, and these changes correlated with signatures observed across all spectroscopic probes. The results reveal that the seed layer both introduces disorder into the MoS2 channel and modifies the interfacial charge environment, controlling charge transfer between HfOx and MoS2. Optical spectroscopy shows that the on-current tracks seed-induced disorder, whereas X-ray photoelectron spectroscopy indicates that the threshold voltage correlates with shifts in the local electrostatic environment associated with interfacial charge transfer. Better performance was obtained with ultrathin 0.2 nm Ta-seed layers deposited under oxygen-poor conditions, which limit deposition-induced damage while facilitating charge transfer. These findings identify seed-layer engineering as a key strategy for controlling disorder and interfacial doping in MoS2 devices and establish multimodal spectroscopy as a practical approach during fabrication for process development and monitoring.

The attractive properties of Two-Dimensional (2D) materials and Transition Metal Dichalcogenides (TMDs) hold significant potential for their use in the next generation of highly-scaled electronic devices. Despite remarkable technological improvements in the integration of this class of materials, the understanding of the carrier transport in these systems and of the possibilities to optimize the dielectric environment still demands in-depth study to reach the performance required by the next technological node. In this work we analyze the impact of the dielectric environment on the carrier transport in mono-layer (ML) MoS2 MOSFETs by employing low temperature Hall and transport measurements on dual-gate Hall bars structure fabricated with different top dielectric stacks. We demonstrate a clear difference in the temperature scaling of the maximal Field-Effect (FE) mobility values, pointing to fundamental differences in the mobility limiting mechanisms that can be attributed to variation in the remote phonon scattering for devices with different dielectric layers.

While cryogenic-temperature subthreshold swing (SS) in crystalline semiconductors has been widely studied, a careful study on the temperature-dependent SS in amorphous oxide semiconductors remains lacking. In this paper, a comprehensive analysis of the SS in thin-film transistors with an amorphous indium-gallium-zinc-oxide (IGZO) channel at temperatures from 300 K down to 4 K is presented. Main observations include the following: (1) at room temperature (300 K), the devices exhibit a SS of 61 mV/dec and a low interface trap density of <1011 cm−2. (2) A SS saturation around 40 mV/dec is observed between 200 and 100 K. It is well explained by the electron transport via band tail states with exponential decay (Wt) of 17 meV. (3) At deep cryogenic temperatures, the SS increases significantly, exceeding 200 mV/dec at 4 K. Such high SS values are actually limited by the measurement current range, confirmed by Id − Vg simulations based on the variable range hopping model. This work not only elucidates the SS behavior in amorphous IGZO devices but also provides a deep understanding of the physical mechanisms of electron transport in amorphous semiconductors.

The attractive properties of 2D materials and transition metal dichalcogenides hold great potential for their use in future, ultra-scaled electronic applications. Although growth processes are increasingly trending towards highly scalable, industry compatible procedures, a fast, reliable, and efficient characterization method for pristine samples is still missing. In this study, we propose the use of back-gated micro four-point probe (M4PP) as a qualitative characterization technique for the early screening of pristine samples. We develop a custom procedure to probe MoS2 samples with different numbers of layers and grain orientations, showing the effects of probe landing and giving an interpretation of the electrical contact between the probe pins and the material. Using the M4PP data we employ a simple and effective parallel capacitor model to extract the charge carriers' concentration (nc) and the field-effect mobility (mu FE). The model is then tested by comparing it with data obtained from back-gated field-effect transistors manufactured on the same material. The comparison provides a striking qualitative similarity, proving the usefulness of back-gated M4PP as characterization method for MoS2 samples.

While we demonstrate a back-gated (BG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) transistors with a nearly ideal subthreshold slope (SS) ~ 60 mV/dec. However, SS degrades when a top-gated (TG) configuration is implemented. The energy distribution of traps inferred from temperature-dependent (T = 4 K - 300 K) and multi-frequency (f = 1 kHz - 100 kHz) admittance measurements, reveals a much higher trap density in TG devices. By analyzing the impact of each process step and conducting forming gas anneal (FGA) experiments, we reveal the role of hydrogen in the deterioration of the SS in the IGZO-based transistors.

The knowledge of energy band alignment in heterojunctions with atomically thin transition metal dichalcogenides (TMDs) is critical for their use in advanced electronic and optoelectronic devices. Despite considerable efforts, the measurement of energy band offset across heterojunctions has been challenging, especially for van der Waals bonded stacks. Key obstacles are related to the scarce and often inconsistent information regarding the bandgap of the TMD layer and the offset between the conduction and valence bands, which is usually inferred from different measurement techniques and samples. To overcome this obstacle, we report combined internal photoemission (IPE) and photoconductivity measurements from 3-monolayer (ML) MoS2 films, grown by chemical vapor deposition on sapphire and transferred onto HfO2-covered silicon. We compare the spectral threshold of electron IPE in this heterostructure with IPE data from the Si/HfO2 interface, yielding the value of the electrostatic potential variation. To improve band offset predictions, we examine the applicability of the classical electron affinity rule by deriving characteristic energies. Our results show that electronic properties at 2D TMD/insulator interfaces depend on the interface processing prior to the 2D material transfer, allowing for the modification of band offsets by adjusting the interface. Furthermore, the measured photoconductivity spectra of 3ML MoS2 allow us to evaluate the bandgap of the TMD layer, which, combined with the IPE barriers, establishes the interface band diagram of a heterojunction. The presented IPE-based experimental approach can be extended to other two-dimensional TMDs for determining the corresponding band alignment schemes. It evaluates the impact of processing, such as solvent-based MoS2 transfer, which introduces a dipole and alters band alignment.

The recent progress in nanosheet transistors has established two-dimensional (2D) semiconductors as viable candidates for future ultra-scaled electronic devices. Next to reducing contact resistance, identifying good gate dielectrics is a fundamental challenge, as the dielectric/channel interface dramatically impacts virtually all performance parameters. While several promising gate dielectrics have recently been reported, the evaluation of their quality and suitability is often fragmentary and focused on selected important performance metrics of the gate stack, such as the capacitive gate control, leakage currents, reliability, and ease of fabrication and integration. However, identifying a suitable gate stack is a complex problem that has not yet been approached systematically. In this perspective, we aim to formulate general criteria for good gate dielectrics.

Two-dimensional transition metal dichalcogenides (2D TMDs), such as MoS2 and WS2, have emerged as promising channel materials for future generation transistors. However, carbon-based surface contaminants pose a significant challenge in the formation of high-quality metal-oxide-semiconductor gate stacks for 2D TMDs. Carbon-based surface contaminants are known to be present even on directly grown 2D TMDs that have not been in contact with polymers. These organic contaminants affect precursor adsorption during atomic layer deposition (ALD) of gate dielectrics on 2D TMDs and as such the 2D-dielectric interface. This study examines the effectiveness of predeposition annealing in mitigating carbon-based contaminants while maintaining the integrity of a directly grown WS2 monolayer on a SiO2 substrate. We show that a WS2 monolayer on a SiO2/Si substrate remains stable during vacuum annealing at temperatures up to 400 degrees C. Water contact angle measurements and x-ray photoelectron spectroscopy confirm that the surface concentration of carbon starts to decrease at 150 degrees C. Thermal anneal improves the surface coverage of Al2O3 for both conventional chemisorption-based ALD and physisorbed-precursor-assisted ALD processes by facilitating more effective Al2O3 nucleation on the WS2 monolayer. The impact of predeposition anneal on the Al2O3 growth behavior in both processes can be explained by changes in surface contaminant levels. Our results underscore the importance of surface pretreatment in dielectric deposition on 2D TMDs and demonstrate that predeposition anneal is an effective method to enhance ALD-based dielectric deposition on directly grown 2D TMDs.

In this work, we have designed and modeled an integrated plasmonic computing module, which operates at 200 GHz clock frequency for high-end streaming algorithm applications. Our work includes designing the individual optical components (modulator, logic gate, and photodetector) and high-speed electronic driver circuits and integrating the components considering their interactions. We have also holistically evaluated the system-level performance of the computing module, taking into account various factors such as power consumption, operational speed, physical footprint, and average temperature. Through rigorous numerical analyses, we have found that with the existing technology and available materials, the plasmonic computing module can best achieve a bit-error-ratio (BER) of $10^{-1}$ . The performance can be improved by using a high electrooptic coefficient material in the phase shifter and increasing the driver circuit’s swing to greater than 1 V.

CFETs based on 2D materials hold the potential to replace Si as a channel at advanced technology nodes. In this work, gate-all-around (GAA) nanosheet FETs with the monolayer MoS2 channels are presented. The MoS2 monolayer was successfully suspended above the oxide trench of varying lengths. Less than 20% sag was observed up to a trench length of 200 nm. For the first time, a gate-first process, in combination with critical point drying, is introduced to scale down GAA nanosheet FETs to 50 nm channel width and length without introducing damage to the monolayer MoS2. Perfect conformal gate stack deposition on the monolayer MoS2 sheets is achieved by using TMA 'soaking' treatment. The successful demonstration of monolayer GAA 2D nanosheet FET further shows high potential as a basic component for the future 2D CFET chips integration.

Implementing a compact optical integrated circuit by utilizing subwavelength plasmonic devices requires the design of compact and efficient photonic to plasmonic mode converters. Especially for plasmonic multiple-input devices such as logic gates that require multiple converters, the footprint can be largely penalized by the photonic waveguides, which should be considered in the design. In this work, we simulate and benchmark five photonic to plasmonic mode converter topologies for the application of multiple-input plasmonic devices. Our design includes both directional and end coupling schemes of plasmonic waveguide and Si photonic waveguides of wire and slot configurations. We optimize the performance of the converters considering the pitch mismatch between the photonic and plasmonic waveguides, the total footprint, and mode conversion efficiency.

We perform trap density (Dt) extraction through admittance measurements on amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin films using multi-finger MOS structures. We investigate the impact of channel length (Lch) on C-V and G-V characteristics and demonstrate a reliable trap density extraction method in short channel devices. The method is validated for pure and Magnesium-doped a-IGZO (Mg:IGZO). The experimental results are consistent with simulations based on a distributed network model.

Implementing two-dimensional materials in field-effect transistors (FETs) offers the opportunity to continue the scaling trend in the complementary metal-oxide-semiconductor technology roadmap. Presently, the search for electrically active defects, in terms of both their density of energy states and their spatial distribution, has turned out to be of paramount importance in synthetic transition metal dichalcogenides layers, as they are suspected of severely inhibiting these devices from achieving their highest performance. Although advanced microscopy tools have allowed the direct detection of physical defects such as grain boundaries and point defects, their implementation at the device scale to assess the active defect distribution and their impact on field-induced channel charge modulation and current transport is strictly restrained. Therefore, it becomes critical to directly probe the gate modulation effect on the carrier population at the nanoscale of an FET channel, with the objective to establish a direct correlation with the device characteristics. Here, we have investigated the active channel in a monolayer MoS2 FET through in situ scanning probe microscopy, namely, Kelvin probe force microscopy and scanning capacitance microscopy, to directly identify active defect sites and to improve our understanding of the contribution of grain boundaries, bilayer islands, and defective grain domains to channel conductance.

In this work, a self-consistent method is used to identify and describe defects plaguing 300 mm integrated 2D field-effect transistors. This method requires measurements of the transfer characteristic hysteresis combined with physics-based modeling of charge carrier capture and emission processes using technology computer aided design (TCAD) tools. The interconnection of experiments and simulations allows one to thoroughly characterize charge trapping/detrapping by/from defects, depending on their energy position. Once the trap energy distribution is extracted, it is used as input in transient TCAD simulations to reproduce the experimental hysteretic transfer characteristics. Our method is widely applicable to any 2D channel/gate stack combination. Here, it is demonstrated on FAB-integrated devices with AlOx/HfO2 gate oxide. A Gaussian-approximated defect band in the AlOx interlayer centered at a position of about 0.1 eV below the conduction band minimum of WS2 is obtained. Based on this energy position, it is concluded that aluminum interstitial and oxygen vacancies are the defects giving rise to the observed hysteresis. These defects are detrimental to the stability of the studied devices as they are easily accessible by channel carriers during on-state operation. A prominent hysteresis obtained during measurements is consistent with this conclusion.

Atomic layer deposition (ALD) of gate dielectrics on two-dimensional transition-metal dichalcogenides (2D TMDs) is challenging due to their chemically inert surfaces. Although various surface pretreatments can form nucleation sites to facilitate the precursor adsorption, preserving 2D TMDs during the pretreatments and maintaining gate stack quality with the weak 2D TMD/dielectric interface become the main concerns. In this work, we combine physisorbed-precursor-assisted (PPA)-ALD to minimize damage to 2D TMDs with a second interfacial layer for performance enhancement. Ultrathin GdAlO3 interlayers are integrated into 2D TMD gate stacks with PPA-ALD AlOx seeding layers and HfO(2 )top dielectrics. Further, 1-nm-thick and pinhole-free GdAlO3 can be deposited on AlOx -seeded monolayer (1L) WS2 by ALD at 250 degrees C. The material properties of 1L WS2 are preserved, as confirmed by Raman spectroscopy. After the GdAlO3 layer insertion, 1L MoS2 dual-gate (DG) field-effect transistors (FETs) show improved subthreshold swing (SS), field-effect mobility, and I-d-V-g hysteresis without compromising the capacitance-equivalent thickness (CET). The proposed strategy is wafer-scale compatible and extendable to the future nanosheet gate-all-around structures.

In this work, we demonstrate high performance FETs integrated on high density aligned carbon nanotube (A-CNT) arrays and perform statistical analysis. The back-gate pFETs show I-on>1.2 mA/mu m, R-c similar to 91 ohm center dot mu m, whereas the dual-gate pFETs show I-on similar to 800 mu A/mu m, on-off ratio similar to 5 x10(3) at 30 nm channel length (L-ch) and -0.5 V V-d. The impact of gate dielectric, EOT scaling and post-fabrication annealing on the device performance are explored in batch. With process optimization, the on-state performance of dual-gate A-CNT FETs is approaching silicon technology.