Retail investor participation in India's stock market has been increasing, driven by improved access to digital platforms and rising financial literacy. However, this surge leads to higher volatility and exposes investors to significant risks if they lack proper knowledge or experience in market dynamics. To overcome this problem, in this manuscript Retail Investor Prediction in India's Stock Market for Demographic Analysis and Risk Assessment (RIP-ISM-CVSTGCNN) is proposed. The model utilizes financial time-series data from the Tata Consultancy Services (TCS) stock dataset, integrated with investor demographic and behavioral attributes to enable comprehensive analysis. The data are pre-processed utilizing Implicit Unscented Particle Filter (IUPF), which is employed to clean the data. Then the pre-processed data are fed into a Complex-Value Spatio-Temporal Graph Convolutional Neural Network (CVSTGCNN) to forecast demographic factors along with a quantitative risk score that reflects the investor’s financial risk level. The proposed model is evaluated using multiple performance metrics, including precision, accuracy, sensitivity, specificity, F1-score, and AUC. Results show that the RIP-ISM-CVSTGCNN method achieves an accuracy of 97.3%, precision of 96.3%, sensitivity of 96.3%, specificity of 96.3%, F1-score of 96.6%, and an AUC of 0.97. Comparative analysis with existing methods, including Multi-Granularity Spatio-Temporal Correlation Networks for Stock Trend Prediction (MGSTCN-STP-GNN), Black Swan event-based hybrid model for Indian stock markets’ trends prediction (ISMT-1DCNN), and Series decomposition Transformer with period- correlation for stock market index prediction (SDTPC-SMI-RNN), demonstrates that the proposed model significantly outperforms all baseline approaches across all evaluation metrics. These outcomes confirm that the proposed framework provides a robust and effective solution for integrated demographic prediction and risk assessment, enabling improved financial decision-making in stock market analysis.
Non-volatile memory (NVM) technologies, particularly Multi-Level Cell (MLC) NVMs, offer significant potential for increasing memory density. MLC NVMs provide a tradeoff between write latency and retention time, where faster writes/stores result in lower retention and slower writes yield higher retention. However, limited work has been done to validate and prototype NVM-based systems in hardware, leveraging this tradeoff at the system level. In this paper, we present a novel memory controller architecture and a RISC-V instruction set extension to optimize MLC NVM write operations by balancing speed and retention time. Our custom NVM controller, built around a finite state machine with an AXI memory-mapped interface, efficiently manages read/write operations with enhanced burst transfers, minimizing latency. Additionally, we introduce a fast-store instruction in RISC-V to increasing write performance while addressing retention limitations. Further, we design a dedicated AXI slave peripheral that supports bit-significance-aware writes: critical bits (e.g., MSBs) are written using slower, high-retention writes, while non-critical bits (e.g., LSBs) use faster, low-retention writes to help enhance performance without compromising data reliability. These enhancements are implemented in hardware on an FPGA platform. Experimental results show that our controller reduces hardware overhead by 30
This paper describes a low-power body-biased StrongARM (SA) latch comparator with low kickback noise, under a supply of 0.9 V for high-speed analog-to-digital converter design applications. To improve the speed of the SA latch comparator, a novel low-power clocked forward body biasing (CFBB) technique based on the auxiliary transistor technique is proposed. Moreover, the proposed CFBB SA latch comparator is compared with the prior conventional CFBB and the improved CFBB SA latch comparators. This work is significant because circuits have been implemented with layouts using a triple-well process. Their parasitic extraction (PEX), post-layout simulation and pre-layout simulations are performed in 45-nm CMOS technology. The proposed CFBB exhibits the best power, delay, offset and kickback noise performance in both pre-layout and post-layout simulations. The proposed CFBB SA comparator achieves a power saving of 17% and a speed improvement of 24% compared with the improved CFBB SA latch comparator. In terms of kickback noise, the proposed CFBB gives only 19.22 [Formula: see text]A, which is 42% less than the improved CFBB SA latch comparator at 1 GHz frequency. Finally, for the proposed CFBB SA latch comparator, a Monte Carlo simulation is performed for 500 samples, which gives an input-referred offset of only 2.90 mV.
Recognition of Telugu handwritten texts is challenging because the script has intricate morphology, different salient character combinations and predominant dimensions. Existing techniques and methodologies, such as traditional conformist machine learning and deep learning, do not adequately solve these Telugu language script problems and usually only provide poor accuracy and limited scalability. This paper proposes a hybrid differential evolution neural network that will help to improve ameliorate feature selection and classification of Telugu handwritten characters, such as compound names such as Guninthamulu and Othulu. The new model takes advantage of Kingpin Differential Evolution’s superior advantages to optimize features dynamically, eliminating redundancy and preserving information necessary for accurate recognition. An exhaustive encyclopedic set of 1,924 Telugu characters, comprising different types of writing, was created and utilized for the testing of the proposed model. The findings show that the proposed model provides a highly consistent accuracy of 98%, far surpassing current methods. The active feature selection system not only increases accuracy, but also boosts the model’s scalability to accommodate various handwriting patterns and multidimensional character sets. This research contributes to a revolution in handwritten text recognition for scripts with low representation and fills the gap in dataset coverage, feature augmentation and recognition performance. This model proposes a hybrid novel architecture to enhance digital archiving, document digitization, and Optical Character Recognition (OCR) for similarly complex languages. Future work might explore the model’s portability to other Indic scripts and further enhance its computation efficiency for large-scale processing.
The vehicle cruise control system (VCCS) is one of the real-world engineering optimization issues that has attracted much attention in regard to the safety and cost-effectiveness concerns. To be effective, a VCC system requires an effective control strategy to work as desired. This work proposes a Tilted Integral Fractional Derivative with Filter plus Fractional Derivative Controller (TIFDNFD) as an efficient controller for VCC systems to tackle the difficult problems connected to effective functioning. The aim is to develop the performance of vehicle cruise control, safety, fuel consumption and comfort with the proposed approach, with minimum settling time and overshoot. By accounting for the inherent nonlinearities and dynamic features of the system, the Secretary Bird Optimization Algorithm (SBOA) method illustrates improved optimization abilities, making it ideal for adjusting the gain of the controller, while simultaneously identifying the optimal value through an evaluation of the integral time square error. The Dual-Stream Multi-Dependency Graph Neural Network (DMGNN) is utilized to predict the optimal TIFDNFD controller parameter. The proposed method’s exceptional ability to develop stability and performance in the temporal domain of VCC systems is confirmed through comprehensive comparisons with existing methods, such as the improved Runge Kutta optimizer (IRUN), Coati Optimization Algorithm (COA) and Arithmetic Optimization Algorithm (AOA), achieving a settling time of 0.9893[Formula: see text]s and a rise time of 0.6549[Formula: see text]s based on present simulation results using the MATLAB platform.
Computing in memory requires more memory space to maintain its stability in hardware components. Due to instability and decreasing power supply voltages in Static Random-Access Memory (SRAM), cell reliability has become a major concern in terms of memory performance and power consumption. Traditionally, SRAM cell size has occupied more memory and consumed more power. To overcome this, a novel Compute in Memory Accelerator with Diagonal shift (CIM-AD) is proposed to reduce memory space and power consumption. The proposed 10-Transistor 2-Capacitor (10T2C) cell is designed for an SRAM array. The proposed 10T2C cell in CIM-AD reduces the memory usage by using a diagonal shift with the sparse method. Diagonal shift is used in the SRAM cell to perform weights in the convolutional layer. To reduce the zero weights in the diagonal shift, a sparse matrix is used. Finally, the memory usage is reduced by using the proposed CIM-AD. The proposed CIM-AD provides high performance in the CIFAR-10 dataset images with lower power consumption. The proposed CIM-AD improves throughput and reduces static power. The proposed SRAM 10T2C cell in the SRAM array keeps data performance high in application requirements. The proposed design achieves better performance by reducing memory usage by 6.25% and power consumption by 52.26%. Further, the proposed CIM-AD in the CIFAR-10 dataset reveals an accuracy of 92.67%.
Photovoltaic (PV) systems convert solar energy into electrical power, providing sustainable and clean energy solutions. However, these systems face critical challenges such as low voltage output and unstable performance due to continuously changing sunlight and temperature conditions. This paper proposes a high-efficiency PV energy conversion system based on an Ultra-Lift Luo Converter (ULLC), designed to overcome the voltage limitations of conventional PV systems. The converter ensures high voltage gain, making it suitable for low-voltage PV sources. A fuzzy PID-D 2 (Proportional–Integral–Derivative second derivative) controller is implemented to provide precise output voltage regulation and enhanced dynamic response. To further improve control accuracy and system stability, the controller parameters are optimized using the Adaptive Siberian Tiger Optimization (STO) algorithm, a recent nature-inspired metaheuristic based on the hunting behavior of Siberian tigers. Additionally, the system integrates a Maximum Power Point Tracking (MPPT) strategy to ensure maximum power extraction from the PV array under all operating conditions. MATLAB Simulation results validate the proposed system, demonstrating improved voltage gain, reduced settling time and enhanced system stability under varying solar irradiance and load conditions. The combination of ULLC, PID-D 2 control and STO-based tuning presents a novel and robust solution for high-performance renewable energy systems.
This article proposes an optimized Dual Stream Spectrum Deconvolution Neural Network for Radarbased Human Activity Recognition (DSSDNN-RHAR) for identifying human actions in real time. Range-Doppler maps are transferred into a Dual Stream Spectrum Deconvolution Neural Network using low-cost frequency-modulated continuous wave (FMCW) radar. The system’s power source is an edge device. The findings indicate that the system has a 98.2% accuracy rate and an inference time of 2.95 seconds for five human motions. In an indoor safety application, sounding an alarm when a dangerous action takes place is an important component. As a result, performance during binary classification that is, fall versus non-fall activities is also evaluated, with a 99.8% accuracy rate and a 4% false-negative rate. The edge system’s energy precision ratio is evaluated to ascertain the optimal trade-off between accuracy and computational expense. The system achieves a ratio of energy precision of 1.04, when an optimal proportion would be close to zero.
By addressing the stringent demands for high speed, low latency and signal integrity in optical interconnects for AI data centers, this paper proposes a 25 Gbps low-noise Transimpedance Amplifier (TIA) with a gain-enhancement technique, realized using [Formula: see text] SiGe BiCMOS technology. Targeting the characteristics of high-density interconnection within AI clusters, this design effectively extends the bandwidth by employing the inductor peaking technique; the adjustable gain-enhancement technique is utilized to reduce the equivalent input noise, thereby ensuring the accuracy of massive model parameter transmission; a fast response is achieved through adaptive current extraction at the input to accommodate AI low-latency communication. Furthermore, it integrates a DC cancellation technique with feedforward and an Received Signal Strength Indicator (RSSI) circuit. A limiting amplifier incorporating a single-ended-to-differential conversion stage, followed by an output buffer, is cascaded in the back end. Test results show that the main TIA achieves a transimpedance gain of 62.6[Formula: see text]dB[Formula: see text] and a [Formula: see text]3 dB bandwidth of 20.3[Formula: see text]GHz; the equivalent input noise current is as low as [Formula: see text] at a 25[Formula: see text]Gb/s operating rate, and the power consumption is only [Formula: see text] under [Formula: see text] supply voltages, making it suitable for large-scale parallel AI optical interconnect applications.
Three-station Time-of-Arrival (TOA) positioning technology holds significant application value in electronic reconnaissance and unmanned aerial vehicle tracking. However, TOA measurements in real-world environments are often affected by non-line-of-sight propagation and synchronization errors, making it challenging to accurately obtain the system's noise statistical characteristics. Traditional Kalman filtering (KF) heavily relies on precise system models and noise parameters; when the pre-set noise covariance mismatches the actual environment, positioning accuracy significantly degrades. To address this issue, this paper proposes a deep Kalman network (KalmanNet)-assisted positioning algorithm based on unsupervised learning.The basic idea is that: encapsulating environmental priors and noise distributions into GRU model parameters, the Kalman Gain could be calculated based on observation variables and dynamically updated state variables. This algorithm adopts a hybrid architecture combining model-driven and data-driven approaches. To avoid performance degradation caused by the inability to collect samples or discrepancies between the training data and the real-world environment, we employ an unsupervised training method. Unlike supervised learning that relies on true state values, this paper designs an unsupervised loss function based on observation innovations, optimizing network parameters through backpropagation. Experimental results demonstrate that, even with only observation data and no true system states, the proposed algorithm can predict target states in real time. Its positioning accuracy outperforms traditional Kalman filtering and exhibits strong robustness across varying noise levels.
The process of predicting crop yield in Indian states includes the estimation of the quantity of crops that will be harvested in certain places. Data analytics is employed to predict yields by incorporating many factors such as historical records, weather patterns, soil conditions, and agricultural methods. An inherent limitation of conventional crop production prediction techniques for Indian states is their dependence on basic models that frequently fail to consider the complex nature of agricultural systems. These techniques may have difficulties in capturing the intricate interaction among many elements that impact agricultural yields, resulting in less precise projections. This study proposes the Bi-Directional Feedforward Q-Network (BiFFQ) model as a solution to this limitation. The technique of predicting agricultural production encompasses many sequential processes. Initially, data preprocessing is carryout, including Data cleaning and normalizing using methods like Z-score normalization. Then, the execution of feature extraction encompasses a range of statistical, temporal, geographical, climatic, and crop-specific variables. The selection of these characteristics is based on their pertinence to the forecast of crop output. Next, the implementation of feature selection through the utilization of a hybrid algorithm known as Canid Swarm Optimization (CSO), which is the combination of Golden Jackal Optimization (GJO) and White Shark Optimizer (WSO). Finally, the utilization of the proposed model Bi-Directional Feedforward Q-Network (BiFFQ) model to estimate crop production. The proposed model incorporates many functionalities, including Feedforward Neural Network (FNN), Bidirectional RNN, and Deep Q-Network (DQN), to effectively predict crop yields by utilizing the collected characteristics. The proposed model is executed utilizing the PYTHON and its effectiveness is evaluated by metrics including accuracy, precision, F-score, specificity, sensitivity, MCC, NPV, FPR, and FNR. When compared to existing methods, suggested BiFFQ achieves superior accuracy (97.64%) and precision (96.46%).
Cervical cancer is a main public health concern, particularly in low-and middle-income countries. A certain amount of cervical cancer is caused by lifestyle choices. The Human Papillomavirus (HPV) is the sexually transmitted infection that causes the most cervical cancers. But only persistent HPV infections cause pre-cancer and cancer to proceed. Risk-dependent prediction approach aid to stratify female with a higher risk of developing cervical cancer with screened them on a priority basis. An Effective Method for Predicting Cervical Cancer Risk Using Semantic-Preserved Generative Adversarial Networks to Enhance Prediction Accuracy and Model Efficiency (PCC-SPGAN-PAM) is proposed. Initially, data are collected from the UCI dataset. Then collected data are fed in to pre-processing phase. Trusted-Based Distributed Set Membership Filtering (TDSF) is used for data cleaning and missing value is restored for target tracking. Then, the pre-processed data are fed into Quaternion Offset Linear Canonical Transform (QOLCT) to extract the features, including the number of sexual partners, age, deliveries, sexually transmitted infections, tobacco usage, and age at first sexual intercourse. The extracted features are fed into SPGAN for predicting the risk of cervical cancer as positive or negative. PCC-SPGAN-PAM has been developed to detect the risk of cervical cancer dependent on one’s lifestyle choices. The PCC-SPGAN-PAM is selected to arrive at an accuracy of 99.23%. It is effective to relate risk factors and PCC that aid ineffectual prevention with management of cervical cancer. It is implemented in Python. Performance metrics are analyzed with existing techniques like Design with Development of Efficient Risk Prediction Method for Cervical Cancer (ERP-CC), cervical cancer prediction utilizing stacked ensemble approach with SMOTE-RFERF (CCP-SEA), ensemble classification method for cervical cancer prediction utilizing behavioral risk factors (EC-CCP-BRF) techniques, respectively.
An innovative algorithm for developing speed control and power efficiency in electric vehicles (EVs) with brushless direct current (BLDC) motors was presented in this approach. This is accomplished by carefully fine-tuning a fuzzy-PI controller utilizing a mix of fuzzy logic optimization approaches, dynamic weighting strategies, and self-adaptive egret swarm optimization (SA-ESO). The random walk with the conventional ESO has been modified to a Cauchy random walk, and the fuzzy-PI controller utilizes a sigmoidal membership function (MF). The controller is tuned to balance energy consumption and speed accuracy when considering several road conditions. To accommodate road gradients and permit the controller to adjust to varying terrain, dynamic weighting is termed a significant innovation. However, energy efficiency, smooth acceleration, speed control, and controller gain adjustments were all optimized simultaneously by a multi-objective optimization algorithm. The best controller parameters were found by effectively exploring the solution space utilizing Red Fox Optimization (RFO). The suggested strategy accomplishes adaptive speed control, improving energy efficiency and accuracy, by incorporating real-time road gradient data. The fuzzy-PI controller’s parameters are dynamically modified using an objective function that takes speed error, smoothness criteria, and energy consumption into account. Compared to conventional PI as well as fuzzy controllers, an optimized fuzzy-PI controller exhibits better stability, quicker convergence, and a lower mean squared error (MSE) in speed control. A more effective and reliable EV control system is the outcome of this all-encompassing strategy, which improves overall performance and lessens environmental impact.
Borrower credit risk assessment plays a critical role in the stability of financial institutions, yet the accuracy of existing models is often constrained by the mixed processing of categorical and continuous features, which differ fundamentally in data characteristics. To address this issue, this paper proposes a novel credit risk assessment model named GTEMG, which integrates a Gated Transformer (Gated-Trans) and an Enhanced Mapping Gated Multi-Layer Perceptron (EM-gMLP). The methodology consists of four steps. First, categorical features are embedded into dense vectors, while continuous features are normalized. Second, a GatedTrans module with a Gaussian Gating Unit (GaGU) extracts high-order nonlinear interactions among categorical features. Third, the resulting context embeddings are concatenated with normalized continuous features. Fourth, an EM-gMLP module with Joint Feature Mapping (JFM) captures both sample-wise and feature-wise interaction information. Finally, a linear layer outputs the credit risk score. Experiments are conducted on three benchmark datasets - German Credit (GC), Australian Credit Approval (AC) and Japanese Credit (JC) - with evaluation metrics of Area Under the Curve (AUC) and Kolmogorov-Smirnov (KS) statistic. The proposed GTEMG model achieves AUC and KS values of 85.49% and 62.42% on GC, 98.31% and 94.59% on AC and 90.28% and 69.82% on JC, respectively, outperforming state-of-the-art tabular data models. It is demonstrated that the proposed method is effective and reliable in credit risk assessment.
A low-noise low-offset rail-to-rail amplifier with full-band frequency compensation is presented in this work. To balance stability, power consumption and size performance, the design realizes full-band frequency compensation by adopting an enhanced hybrid topology, in which transconductance capacitance feedback compensation (TCFC) is nested within a multipath nested Miller compensation (MNMC) topology. The proposed design employs a three-stage amplifier to improve DC-gain, using parallel complementary differential pairs with current feedback loop and a class-AB stage to achieve stable rail-to-rail input and output. The PMOS-dominant differential transistor pairs of input stage are operated in sub-threshold region, enabling lower input-referred thermal noise and much lower power consumption. Furthermore, a source degeneration structure is incorporated to further suppress thermal noise, along with a trimming logic to minimize the offset voltage. Finally, a slew-rate enhancement (SRE) circuit is further implemented to ensure that large output currents can be supplied under low quiescent current conditions, thus enabling a full rail-to-rail output swing. Fabricated in 0.18 mu m CMOS process technology, the layout occupies an area of 890 mu m & times;495 mu m. Operating under a 5V power supply, the pre-layout simulation results demonstrate that the amplifier achieves rail-to-rail input/output functionality with an open-loop gain of 154dB, phase margin of 69.53 degrees, and gain-bandwidth product (GBW) of 9.9MHz. The equivalent input noise is 8.5nV/Hz at 1kHz, with a common-mode rejection ratio of 109.456dB. The power supply rejection ratios is 114.697dB. The measured positive and negative slew rates reach 7.35V/mu s and 8.37V/mu s.
A new generation of high-performance computing systems is enabled by quantum technology, which offers unprecedented processing speed and energy efficiency. This manuscript investigates the implementation of Reversible Programmable Logic Arrays (RPLAs) on real quantum platforms, emphasizing testability and noise resilience as primary design objectives. We present a novel low-cost RPLA architecture capable of realizing multi-output Exclusive Sum-of-Products (ESOP) functions. An algorithm is used to sort and optimize the ESOP product terms, reducing design complexity while supporting energy-efficient computation through reversible logic. The proposed RPLA demonstrates substantial improvements in key quantum primitives and includes enhanced testability features along with an extensive noise analysis performed on Qiskit quantum computing. The noise evaluation incorporates widely used quantum error models, including bit-flip, amplitude damping, depolarizing, and phase damping, to assess the robustness of the design under realistic operating conditions. Furthermore, a Quantum Equivalent Circuit (QEC) is developed, and a comprehensive testability analysis is conducted using the IBM Quantum Experience (IBM-QE), covering Single Gate Missing (SGM) and Single Control-Point Missing (SCP) faults to ensure robust fault detection. Experimental results obtained from IBM-QE indicate that the proposed RPLA achieves improvements of 34.43% in Gate Count (GT), 54.70% in Garbage Outputs (Gar), and 36.72% in Quantum Cost (QC) compared with existing methods. These enhancements highlight the potential of the proposed architecture for practical, sustainable, and energy-efficient quantum computing applications.
Multiple cell upsets are causing major problems with the reliability of memories exposed to radiation environments (MCUs). More complicated error correction codes (ECCs) are frequently employed to safeguard memory and stop MCUs from corrupting data, but their primary drawback is that increasing delay overhead is necessary. Recently, various ECC codes have been introduced however, the primary issue is that only two-to-five-bit errors are corrected faults can be corrected. To overcome these challenges, a novel Contiguous Multiple Bit Upset Mitigation (CMBUM) model has been proposed for data protection in SRAM memories. The proposed CMBUM model utilized Interleaved Counter Matrix (ICM) code which uses a combinational ones counter and parity generator to reduce delay overhead and improve memory reliability. CMBUM achieves maximal correction coverage by performing parallel 8-bit error correcting considerably. The proposed ICM code integrates the ICM code into the decoder and uses 32-bit data as input to the encoder in order to reduce the number of superfluous bits. The proposed method is implemented using a 45-nm library, and it is compared to the current approach, which provides better error protection with minimal redundancy and low overhead. Evaluation findings show notable reductions in area, power, and delay when comparing the proposed CMBUM technique to the existing technique, which can correct double and 8-adjacent faults.
Electromagnetic interference (EMI) is one of the main issues in brushless direct current (BLDC) motors, which harms efficiency, reliability and international EMI regulations. Traditional methods of suppression are not always flexible and deteriorate performance, which requires solutions of high quality. To solve this, a new system, the enhanced EMI resilience optimization system (EEROS), is proposed, which combines three new methods: active common mode swarm-enhanced EMI mitigation system (ACS-EMS), adaptive power management EMI control system (APM-ECS) and adaptive spread spectrum-filtered genetic EMI suppression (ASSF-GES). These techniques use spread spectrum modulation (SSM), active EMI filters (AEFs), genetic algorithms (GAs), particle swarm optimization (PSO) and dynamic frequency modulation (DFM) to create dynamic suppression of high-frequency EMI and motor efficiency of 98%, thermal stability of 59 degrees C and responsiveness of 98%. The paper also analyzes how the variations of control parameters affect the EMI suppression and performance trade-offs and proves the existence of a strong and high-efficiency mitigation framework. The proposed system offers a scalable solution to automotive, industrial and aerospace applications and has better EMI resilience, regulatory compliance and operational reliability.
Due to the design of network technologies and technical emergence, the cloud has altered the manner in which data are mutual. It offered persons and organizations several services which facilitate the users to easily access the data and resources. However, the cloud enables huge efforts in ensuring the sharing of data, but there exist security problems which should be addressed. This paper devises a Dwarf Mongoose Whale Optimization (DMWOA) model for performing the key generation. The data sharing model is formed between different entities, such as blockchain, Data User (DU), Data Owner (DO), Attribute Authorities (AAs), Certificate Authority (CA), and Cloud Service Provider (CSP). The data sharing model embedded with authentication is necessary for improving the security of the cloud in blockchain. In addition, the authentication approach involves several processes, namely system initialization, registration, key generation, authentication, Data Access control, encryption, token generation, and decryption. Besides, it builds joint trust among different AAs using blockchain, and it uses smart contracts. The method outperformed with a small memory of 96.00MB, detection rate of 0.929, and computation time of 7.002s.
