In this brief, a frequency modulation (FM) based isolated gate driver (IGD) for GaN HEMT is proposed and implemented in TSMC 0.18 μm BCD. The FM-based gate driving scheme powers the secondary IC from within the IGD, eliminating the need for an external isolated secondary power supply in conventional IGDs. The driving characteristics of the proposed IGD are evaluated with a 1 nF load and achieves propagation delay below 120 ns and maximum switching frequency of 2 MHz. The proposed IGD consumes 246 mW and 330 mW from the 6 V primary power supply when operated at a switching frequency of 250 kHz and 2 MHz, respectively. Furthermore, a multiple-pulse test is performed with the proposed IGD, switching an Infineon GS-065-008-1-L E-mode GaN HEMT (QG = 1.6 nC,RDS,on = 225 mΩ) at a supply voltage of 400 V. The proposed IGD demonstrated the possibility of combining the signal and power transmissions, while providing a constant power supply to the secondary side.
This paper introduces a transformer-based dual-path noise-canceling low-noise amplifier (LNA) operating across 17.4-to-39.5GHz in a 28nm CMOS process. Compared with classic noise-canceling LNAs that rely on either a feedforward transformer only in the common gate (CG) amplifier or a feedback only in the common source (CS) amplifier, the proposed design employs both feedforward and feedback transformers to improve the design trade-off including noise figure and bandwidth. The LNA fabricated in a 28nm CMOS process occupies a core chip area of 0.21mm2. It achieves a 2.7-4.3dB NF within a 17.4-39.5GHz operation frequency range with 41mW power consumption at 1V power supply. The peak gain is 23dB and the S11 remains below -6dB. The measured input-referred 1-dB compression point (IP1dB) and input-referred third-order intercept point (IIP3) are -14dBm and -3dBm at 32GHz, respectively.
The number theoretic transform (NTT) and its inverse (INTT) are key computational kernels in the post-quantum digital signature schemes ML-DSA and FN-DSA. Supporting different transform lengths within a unified architecture requires configuration switching, while mismatched arithmetic demands across operating modes can lead to underutilization of shared resources. This brief develops a runtime-configurable high-radix Winograd NTT/INTT core that supports two moduli, three transform lengths, and both forward and inverse transforms within a single hardware instance. A context-packed multi-issue (CPMI) architecture is further proposed to improve throughput through stage-wise batching and multiplication-resource remapping without increasing the number of DSP blocks or memory banks. The proposed design is placed and routed on a Xilinx XCVU9P FPGA and operates at 312.5 MHz. Across the three configurations, it achieves 1.61×–2.15× the baseline throughput, while reducing the normalized area–time product (ATP) by up to 36.0% compared with existing designs.
The multi-bit/cycle SAR ADCs improve conversion speed significantly compared with single-bit/cycle architectures, yet suffer from exponentially increased comparator and DAC overhead, resulting in large input loading, high area cost, and severe noise issues. This brief presents a 2.6b/cycle time-interpolator-assisted SAR ADC, which reduces the number of comparators from 5 to 3 and employs only one reference DAC. Implemented in a 28-nm CMOS process, the proposed 8-bit 16×-interleaved SAR ADC employs off-chip digital fine background timing skew calibration to effectively suppress interleaving-induced spurs. Measurement results show 41.9-dB SNDR and 50.8-dB SFDR at near-Nyquist input after calibration. The overall power consumption is 96.5 mW, yielding a Walden FoM of 118.6 fJ/conv.-step.
This work presents a controlled-initialization lower-bound error (LBE) framework for finite-time estimation of the largest Lyapunov exponent (LLE) in chaotic electronic circuits. A prescribed condition is imposed on a controlled state variable of two nearby realizations of the same nominal circuit, and the LLE is estimated from the initial LBE growth over a selected divergence window. The framework is implemented in Simulink and hardware using jerk and Chua circuits. The simulation and hardware estimates differ by 2.85% for the jerk circuit and 0.40% for Chua’s circuit, while comparison with the Wolf and Rosenstein methods yields relative differences between 0.12% and 2.85%. Repeated experiments across different initialization levels, together with sensitivity analysis over neighboring window-selection parameters, support the repeatability of the finite-time estimates under the analysed conditions. The proposed circuit-level approach provides direct LLE estimation from measured divergence without requiring phase-space reconstruction or nearest-neighbor tracking.
