Many hardware accelerators have been proposed to accelerate sparse computations. When these accelerators are placed in the nodes of a large cluster, distributed sparse applications become heavily communication-bound. Unfortunately, software solutions to optimize network communication are inefficient. In this paper, we introduce novel hardware mechanisms to optimize network communication in distributed sparse computations. Our proposal, called NetSparse, consists of four mechanisms. Communication is offloaded to new processing units in the NIC that support efficient remote indexed gather operations, minimizing host-NIC communication. Moreover, these units have the ability to identify and eliminate redundant requests, which minimizes traffic. Further, new hardware modules in the NICs and switches concatenate multiple requests with the same destination node in a single packet, saving traffic and header overheads. Finally, switches are augmented with a hardware cache that stores fetched data from remote racks, making it available to all the nodes in the local rack on demand. Our evaluation on a simulated 128-node cluster with per-node sparse accelerators running sparse workloads reveals that NetSparse improves performance substantially. When the cluster uses traditional software-based communication, the workloads run only 3x faster than on a single-node system; when it is augmented with the NetSparse hardware, the workloads run 38x faster than on the single-node system—attaining more than half of the performance of an ideal system that has no communication overheads.
To scale ILP, designers build deeper and wider out-of-order superscalar CPUs. However, this approach incurs quadratic scaling complexity, area, and energy costs with each generation. While small loops may benefit from increased instruction-window sizes and large loops may see speedups via thread-level parallelism across cores, there remains unexploited medium-granularity parallelism. We propose LoopFrog to tap into this potential by bringing thread-level speculation schemes into the modern era. LoopFrog runs multiple loop iterations from a single thread in parallel within the microarchitecture. The core can spawn future loop iterations as new microarchitectural threadlets based on compiler-inserted hints, which can leapfrog execution beyond the parent thread's instruction window, exposing a new, medium-grained parallelism, orthogonal to traditional ILP and TLP. LoopFrog monitors data dependencies between executing threadlets, forwards data for true dependencies and squashes speculative threadlets on ordering violations. Using an LLVM-based compiler to insert hints, we achieve a geometric mean loop speedup of 43%, translating to whole-program speedups of 9.2% on SPEC CPU 2006 and 9.5% on SPEC CPU 2017 benchmarks, with only modest area and power overheads.
Fully Homomorphic Encryption (FHE) allows for direct computation on encrypted data, preserving privacy while enabling outsourced processing. Despite its compelling advantages, FHE schemes come with a significant performance penalty. Although recent cryptographic advances have introduced promising optimization technologies to mitigate computational burden, FHE accelerator designs face significant challenges in deploying these algorithmic optimizations. These challenges stem primarily from divergent computational precision requirements and escalating onchip memory demands, leading to mismatches between algorithm and hardware constraints. We propose HAWK, an FHE acceleration solution based on algorithm-hardware co-design. We begin with an in-depth analysis of the original key decomposition switching approach (KDS), identifying the main limitations of applying it to mainstream FHE accelerators. To address these issues, we propose the fixed-word key decomposition switching method (FW-KDS), significantly reducing computational overhead and memory requirements by up to 58%. We demonstrate how to effectively integrate this method into fixed-word accelerator designs and introduce several further optimizations. To address the expensive rounding operation inherent in the KDS method, we develop a new computational approach that reduces hardware costs while completely eliminating rounding errors. Furthermore, we adapt the underlying architecture to align with the computational demands of our algorithmic optimizations. To the best of our knowledge, this is the first exploration of deploying the KDS method in the fixed-word hardware accelerator. Experimental results demonstrate that HAWK achieves up to a 1.45x performance improvement with only a 4% area increase.
Task-parallel programming models enable programmers to extract parallelism from irregular applications. Since software-based task-parallel runtimes impose crippling overheads on fine-grain tasks, architects have designed manycores with hardware support for task management. These hardware task-parallel systems can scale challenging workloads to hundreds of cores, but fail to use conventional prefetchers due to short (100-cycle) tasks. Lacking prefetching, they often expose DRAM latency to applications, fumbling the performance gains of hardware. We present the Task-Seeded Prefetcher (TSP) and Memory Response Task Scheduler (MRS), a symbiotic pair that boost performance in general-purpose task-parallel hardware. TSP learns and prefetches the data-access pattern of each task function, seeded with its descriptor that is queued by the task scheduler. MRS augments the baseline task-to-core dispatch policy by using prefetch status from TSP to optimize core utilization. Together, TSP and MRS provide speedups of up to 3.1x (gmeans up to 1.4x) across 13 benchmarks on 256-core task-parallel systems that were already 3-60x faster than parallel software.
Pattern matching is a key operation in unstructured data analytics, commonly supported by regular expression (regex) engines. Bit-parallel regex engines compile regexes into bitstream programs, which expose fine-grained parallelism and are well-suited for GPU execution. A straightforward strategy executes each bitstream instruction sequentially, processing all data blocks in a loop. However, this execution suffers from poor data reuse and high memory consumption, limiting throughput. Our key insight is to adopt an interleaved execution model, where all bitstream instructions are fused into a single loop and executed block-wise. While interleaved execution could improve data reuse, enabling it on GPUs is non-trivial due to cross-block data dependencies. To address this, we introduce 1) Dependency-Aware Thread-Data Mapping, which resolves cross-block dependencies via selective recomputation. We further improve interleaved execution performance with two additional optimizations: 2) Shift Rebalancing, which balances dependency chains to reduce synchronization barriers; and 3) Zero Block Skipping, which exploits bitstream sparsity to skip computation on zero blocks. Together, these techniques make interleaved execution practical and efficient. Experiments on real-world regex benchmarks demonstrate a 19.5x geometric mean speedup over the state-of-the-art GPU regex engine.
Quantized Deep Neural Networks (DNNs) have progressed to utilize sub-8-bit data types, achieving notable reductions in both memory usage and computational expenses. Nevertheless, the efficient execution of sub-8-bit convolution operations remains insufficiently optimized, especially in the context of Single Instruction Multiple Data (SIMD) architectures. This paper introduces HiPACK, which takes the packing for efficient convolution as foundation to reduce the required number of operations, and address the challenges of SIMD incompatibility in sub-8-bit direct convolution by decoupling the unpacking phase from multiplication operations, optimizing the caching of intermediate data, determining the ideal segmentation, and employing a dual interleaved register (DIR) mechanism to facilitate parallel multiplication through SIMD. Collectively, these optimizations significantly enhance computational efficiency and diminish operational overhead. Evaluation on the BCM2711 ARM processor reveals speedups of up to 4.6x compared to floating-point calculations and 1.7x when measured against state-of-the-art solutions, thus accelerating model inference. Our implementation is open-sourced and available at: https://github.com/Xtra-Computing/HIPACK.
Modern Graphics Processing Units (GPUs) support virtual memory to ease programmability and concurrency, but still suffer from significant address translation overhead due to frequent Translation Lookaside Buffer (TLB) misses and limited TLB Miss-Status Holding Register (MSHR) capacity. These misses trigger long-latency page table walks and stall memory accesses, degrading overall performance. In this paper, we present LATPC, a novel mechanism that combines TLB prefetching with MSHR compression to accelerate GPU address translation. LATPC leverages the regularity of Virtual Page Numbers (VPNs) across threads within a warp to coalesce TLB misses at the warp instruction level. LATPC then compresses multiple TLB miss requests into a small number of MSHR entries, reducing contention and enabling more efficient resource use. LATPC further improves translation efficiency by batching page table walks based on the identified VPN patterns, which not only reduces the number of page table walk invocations but also increases off-chip DRAM row buffer locality, lowering the latency of memory accesses during translation. Our evaluation using 24 GPU workloads shows that LATPC effectively exploits regularities and localities in address translation requests within a warp, achieving a 1.47x geometric mean speedup over the baseline without TLB prefetching.
As DRAM technology scales down, maintaining prior levels of reliability becomes increasingly challenging due to heightened susceptibility to faults. This growing concern underscores the need for effective in-field fault monitoring and management. Addressing this challenge, this work first introduces a refined DRAM fault classification, derived from the correlation between DRAM addresses and their underlying architectural hierarchies of faulty DRAMs. Building on this classification, we propose a comprehensive memory fault management strategy adequate to each DRAM fault. We further formalize and implement a structured remediation framework, enabling fault-specific mitigation. Utilizing this methodology, we conduct a large-scale field study on DDR4 x4 and DDR5 10x4 RDIMMs, uncovering that over 98% of DDR4 x4 RDIMM faults are tightly coupled with intra-bank architectural characteristics. In particular, we identify that early detection and localized management of faults within 2x2 MATs1-encompassing the vast majority of clustered row faults-are crucial to achieving resilient memory subsystems. We also observe intrinsic correlations among faulty Row Addresses (RAs), indicating unavoidable structural address
With the increasing importance of deep learning workloads, many hardware accelerators have been proposed in both academia and industry. However, software tooling for the vast majority of them does not exist compared to the software ecosystem and innovations proposed for established platforms such as CPUs and GPUs. We observed that the lack of well-defined hardware-software interfaces and correctness testing tools like fast and scalable test oracles (also known as functional simulators) act as significant barriers to adopting these emerging accelerators in the software community. These interfaces and tools are essential in building software such as retargetable compilers and optimized kernels. To bridge these gaps, we first present TAIDL, an instruction specification language that provides novel constructs to describe the instruction set architectures (ISAs) of tensor accelerators. Next, given ISA definitions in TAIDL, we introduce techniques to automatically generate fast and scalable test oracles for diverse sets of accelerators, which are needed for testing software correctness of code that targets pre-silicon hardware designs. Automated generation of such tools reduces the burden on hardware architects and the repeated development efforts required across different accelerator platforms. Further, our techniques allow us to execute these simulators on GPUs, leading to highly scalable simulations. To demonstrate the expressivity of TAIDL, we instantiated several tensor accelerator ISAs with different compute capabilities and memory hierarchies. Further, we show that test oracles generated using TAIDL definitions are orders of magnitude faster and more scalable than existing instruction-level functional simulators, making them suitable for integration into software development cycles. TAIDL is available at https://github.com/act-compiler/taidl.
The traditional Network Interface Controller (NIC) suffers from the inherent inefficiency of the PCIe interconnect with two key limitations. First, since it allows the NIC to transfer packets to the host CPU memory only through DMA, it incurs high latency, the impact of which becomes more pronounced, especially for smallsized packets. Second, it supports neither shared memory nor full cache coherence between the host CPU and the NIC. Therefore, the host CPU can access NIC memory only through MMIO-which provides higher latency and lower bandwidth than cache-coherent memory access-and software is often responsible for managing consistency between the host CPU and NIC memory. Although built on the PCIe interconnect, Compute Express Link (CXL) efficiently addresses these limitations by providing hardware-managed unified memory and cache coherence between the host CPU and NIC memory. This allows the host CPU and the NIC to access each other's memory using load/store semantics, offering low latency and high bandwidth. In this work, we first present a Type-1 CXL-NIC design that replaces slow legacy PCIe transactions with fast CXL.cache transactions for NIC-to-CPU memory accesses. Second, we extend the Type-1 CXL-NIC to a Type-2 CXL-NIC that introduces cachecoherent NIC memory exposed to the host CPU through CXL.mem, which can buffer packets and descriptors1. Lastly, we demonstrate a networking-application co-acceleration by exploiting unique CXL Type-2 device features and near-packet processing on the Type-2 CXL-NIC. Our FPGA-based CXL-NIC prototypes reduce the tail latency of network packet and application request processing by 49% and 39%, respectively, compared to a commodity PCIe-NIC.
As the parameter size of large language models (LLMs) continues to expand, the need for a large memory footprint and high communication bandwidth have become significant bottlenecks for the training and inference of LLMs. To mitigate these bottlenecks, various tensor compression techniques have been proposed to reduce the data size, thereby alleviating memory requirements and communication pressure. Our research found that video codecs, despite being originally designed for compressing videos, show excellent efficiency when compressing various types of tensors. We demonstrate that video codecs can be versatile and general-purpose tensor codecs while achieving the state-of-the-art compression efficiency in various tasks. We further make use of the hardware video encoding and decoding module available on GPUs to create a framework capable of both inference and training with video codecs repurposed as tensor codecs. Building on insights gained from video codecs, we further show that the hardware of the video codecs can be customized and enhanced to significantly improve tensor encoding/decoding throughput without incurring substantial costs, making it a highly effective solution for large-scale model deployment without requiring significant modifications to the existing GPU architecture.
The growing demand for neural network (NN) driven applications in AIoT devices necessitates efficient matrix multiplication (MM) acceleration. While domain-specific accelerators (DSAs) for NN are widely used, their large area overhead of dedicated buffers and low reusability limit cost-effectiveness. Processing-in-cache (PIC) architectures address this by repurposing existing SRAMs in processor caches for MM computation, eliminating dedicated DSA areas while retaining programmability. Despite its potential, PIC designs often overlook fundamental system-level issues, e.g., compactness, programmability, coherence, and scheduling optimization. In this work, we introduce PolymorPIC, a polymorphic architecture designed to accelerate MM directly within the cache using a bit-serial computing pattern. First, we propose a reconfigurable and processor-safe PIC architecture based on homogeneous memory arrays (HMAs), programmed through a meticulously designed interfaces in our software stack. Next, to enable mode switch of cache between cache mode and PIC mode, we develop a coherence strategy that ensures rapid, flexible, and processor-safe PIC. Moreover, we conduct scheduling optimization to maximize the NN acceleration performance of PolymorPIC. Ultimately, the PolymorPIC architecture is implemented on a RISC-V-based system-on-chip (SoC) and successfully end-to-end verified on a validation platform with an operating system running. Evaluation results show that by only introducing 11.5% area overhead for a single-core Out-of-Order processor (BOOM) with 1MB cache, PolymorPIC can improve the energy efficiency (TOPS/W) of multiple NNs by 1543.8x on average. Compared to system-level implementation of using NPU as co-processor (Gemmini), PolymorPIC outperforms it by 3.76x in area efficiency and 3.9x in energy efficiency.
In distributed large model training, the long communication time required to exchange large volumes of gradients and activations among GPUs dominates the training time. To reduce the communication times, lossy or lossless compression of gradients and/or activations can be employed. However, lossy compression of gradients and activations may demand more training iterations to achieve the same model accuracy and cause convergence failure, respectively. Lossless compression, on the other hand, may not reduce the volumes of gradients and activations enough to offset the significant latency associated with compression and decompression on current platforms. To address these challenges, we propose NetZIP, an algorithm/hardware co-design for in-network lossless compression of both gradients and activations. NetZIP consists of two components. (1) NetZIP-algorithm transforms gradients and activations at the bit and value levels to help lightweight standard lossless compression achieve more compression of the gradients and activations. (2) NetZIP-accelerator integrates NetZIP-algorithm with a lightweight lossless compression accelerator within a NIC in a bump-in-the-wire fashion to reduce the compression/decompression latency under the resource constraints. NetZIP-algorithm compresses gradients and activations 40-63 and 43-75 percentage points more, respectively, than heavy standard lossless compression for Llama-3 70B, GPT-3 175B, and Llama-3 405B. NetZIP-accelerator, implemented within FPGA-NICs and connected to commodity servers, provides orders of magnitude lower latency for compression and decompression, respectively, than the lowest latency achieved by the standard lossless compression on current platforms. With greater compression of both gradients and activations, and lower latency for compression and decompression than the standard lossless compression, NetZIP provides 35% lower training time.
Recent breakthroughs in AI reasoning, enabled by test-time compute (TTC) on compact large language models (LLMs), offer great potential for edge devices to effectively execute complex reasoning tasks. However, the intricate inference pipelines associated with TTC pose new efficiency bottlenecks, limiting achievable latency and hindering widespread adoption. Through an in-depth analysis, we identify three key barriers: (1) variable parallelism, characterized by inference-dependent dynamic control flows and varying batch sizes, complicating workload scheduling; (2) branch dependencies, hindering efficient pipelining across sequential reasoning steps; and (3) branch pruning, causing memory fragmentation and irregular data access patterns. Motivated by the memory-bound nature of LLMs and Processing-in-Memory (PIM)'s capability to reduce data movement, we propose ORCHES, a novel GPU-PIM collaborative system specifically designed to address these barriers. ORCHES integrates three key innovations: (1) adaptive workload assignment, dynamically balancing workloads between GPU and PIM units to maximize parallelism despite unpredictable branching; (2) branch-aware pipelining, leveraging speculative execution to substantially reduce inter-step pipeline stalls; and (3) fragmentationaware memory structuring, enhancing data locality and access efficiency through coordinated caching and optimized memory layout reorganization. Experimental results demonstrate that ORCHES achieves average speedups of 4.16x and 3.10x over state-of-the-art (SOTA) GPU implementations for text-based and vision-based reasoning tasks, respectively, without any loss in the accuracy of the original reasoning pipeline.
Security research on modern CPUs has raised numerous concerns in recent years. These security issues stem from classic microarchitectural optimizations designed decades ago, without consideration for security. Stack pointer tracking, also known as the stack engine in recent CPUs, is one such optimization. To investigate the security implications of the stack engine, we reverse engineer its operational details on a number of recent Intel and AMD CPUs for the first time. Our results show the particular microarchitecture-dependent behaviors of the stack engine, such as the conditions under which it needs to synchronize the stack pointer values with the backend. Using these results, we build three primitives called Direct Underflow, Sync+Reload and Prime+Sync+Probe that enable information leakage through the stack engine under different conditions. We use these primitives in the construction of various covert and side-channel attacks, leaking sensitive patient records from a widely-used JSON library as an example. Our mitigation efforts reveal that recent AMD Zen 4 and Zen 5 CPUs include undocumented chicken bits which allow enabling or disabling the stack engine. Using these bits to disable the stack engine, we measure 3.98% and 3.94% slowdown using SPEC CPU2017 on Zen 4 and Zen 5, respectively, prompting the need to consider more secure designs for the stack engine in future CPUs which we also discuss.
Point cloud analytics plays a crucial role in spatial machine vision for applications like autonomous driving, robotics and AR/VR. Recently, numerous domain-specific accelerators have been proposed to meet the stringent real-time and energy-efficiency demands of embedded and mobile platforms. However, most existing point cloud accelerators are kernel-independent hardware architectures, which face significant limitations and struggle to adapt to the rapidly evolving nature of point cloud applications. To address these challenges, we propose PointISA, a novel Instruction Set Architecture (ISA) extension designed for efficient point cloud analytics through architecture and algorithm co-design. First, we incorporate specialized instructions into PointISA for point cloud processing, such as Euclidean distance computation and multidimensional sorting. And then, we present an unified hardware architecture that efficiently executes both PointISA's specialized instructions and conventional matrix multiplication. Finally, we optimize key algorithms like farthest point sampling and k-nearest neighbors, adapting them into parallel multiple-points-to-multiplepoints (MP2MP) patterns that fully exploit the architecture's parallel capabilities while maintaining algorithmic correctness. Evaluation shows that PointISA achieves an average 5.4x speedup and 4.9x improvement in power efficiency across diverse point cloud workloads while incurring a negligible area overhead of 0.9%.
High-performance Last-level Cache (LLC) replacement policies mitigate off-chip memory access latency by intelligently determining which cache lines to retain in the LLC. State-of-the-art replacement policies significantly outperform policies like LRU. However, the effectiveness of these policies is not evaluated on many-core systems with sliced LLCs, which is common in commercial many-core systems. Recent state-of-the-art LLC replacement policies use two seminal ideas: (i) a sampled cache and (ii) a reuse predictor. In a monolithic LLC, there is a single sampled cache and a single reuse predictor. However, these structures must be created per slice with the sliced LLC. We study the interaction between sliced LLC and state-of-the-art replacement policies, identifying a few unexplored interactions. A per-slice reuse predictor makes myopic decisions based on the accesses made to a particular slice, unaware of the global reuse behavior. A trivial solution to this problem is to design a centralized reuse predictor shared by all the LLC slices. However, this will significantly increase interconnect traffic, requiring more bandwidth to access the centralized reuse predictor. Next, we observe that with a sliced LLC, the LLC sets used for the sampled cache do not receive sufficient LLC misses. As these LLC sets drive the decisions of LLC replacement policies, some of the decisions become suboptimal. We propose Drishti, which is designed to improve the effectiveness of LLC replacement policies further. We make a case for two enhancements: (i) a per-core and yet global reuse predictor with a local (per-slice) sampled cache, and argue that there is no need for a global sampled cache, and (ii) a per-slice dynamic sampled cache to improve the utility of LLC sets used for the sampled cache. We evaluate two state-of-the-art LLC replacement policies, Hawkeye and Mockingjay, on four, 16, and 32-core systems with eight, 32, and 64MB sliced LLC. On a 32-core system, Drishti enhances the effectiveness of two state-of-the-art replacement policies, Hawkeye and Mockingjay, by improving performance by 5.6% and 13.2%, respectively, compared to the baseline LRU policy. Without Drishti, Hawkeye and Mockingjay improve performance by 3.3% and 6.7%, respectively.
Transformer-empowered Graph Neural Networks (TF-GNNs) are gaining significant attention in AI research because they leverage the front-end Transformer's ability to process textual data while also harnessing the back-end GNN's capacity to analyze graph structures. Typically, TF-GNNs follow the sequential execution mode, where the front-end Transformer first encodes vertex features, followed by subgraph sampling and subsequent processing by the back-end GNN. However, due to the massive computation workloads of Transformers and the irregular memory access patterns of GNNs, achieving efficient inference for TF-GNNs remains a challenge. Although architectures like FACT and MEGA have been proposed to separately accelerate the Transformer and GNN, they overlook the new opportunities arising from the coupling of the Transformer and GNN. To enable efficient TF-GNNs, we propose HEAT, a heterogeneous architecture with a Neural Processing Unit (NPU) and a DIMM-based Near-Data Processing (NDP). Such a heterogeneous architecture can utilize both the high computational power of NPU and the high internal bandwidth of NDP. To fully unleash the potential of the NPU-NDP architecture, HEAT makes the following three contributions: First, HEAT leverages graph topology to identify the importance of vertices and encodes their features in the Transformer using varying precision accordingly. Second, HEAT gives more flexibility to the execution granularity and execution order of subgraphs in GNN, allowing their DRAM accesses to scatter across different banks and enhancing locality between subgraphs. Third, HEAT decouples the inherent dependency between the front-end Transformer and the back-end GNN by allowing the Transformer to selectively encode only the vertex features required by the current subgraph. This enables concurrent execution of the NPU and NDP, thereby fully exploiting the parallelism of the heterogeneous architecture. Comprehensive evaluations on a wide range of datasets demonstrate that HEAT outperforms the high-performance A100 GPU, the state-of-the-art (SOTA) Transformer accelerator FACT, and GNN accelerator MEGA in terms of execution time and energy efficiency.
The exponential growth of artificial intelligence (AI) has spurred a demand for efficient, scalable computing. While domain-specific accelerators (DSAs) outperform general-purpose GPUs, their closed architectures lead to ecosystem fragmentation. The open RISC-V ISA offers a path to a unified ecosystem, but faces fundamental architectural challenges: the inefficiency of standard extensions for domain-specific workloads and severe memory contention in heterogeneous SoCs. This paper investigates these challenges and proposes a set of evidence-backed design principles for high-performance RISC-V AI accelerators. To this end, we present OASIS, the first commercial terminal AI processor supporting RISC-V tensor extension instructions. Its core innovation is a scalable, multi-core RISC-V Tensor Processing Unit (RTPU) architected with three key principles: a hardware-accelerated data path to solve the im2col bottleneck; a decoupled memory subsystem to eliminate resource contention; and a novel, low-overhead synchronization mechanism that enables near-linear multi-core scaling. The success of this evidence-driven architecture is ultimately validated by an evaluation of the fabricated chip. To demonstrate its versatility, we benchmark its performance across a wide spectrum of representative AI models. Our results consistently show superior performance over leading commercial platforms across key terminal AI scenarios. This outcome is supported by deep-dive analyses including multi-core scaling and multi-model concurrency tests, alongside a Roofline model which confirms high hardware utilization. By submitting our tensor extension for standardization, this work establishes a new, evidence-backed blueprint for an open, scalable, and high-performance AI computing ecosystem.
Transformer acceleration has increasingly emphasized local fusion within isolated submodules, such as multi-head attention (MHA) and softmax. However, as Transformer models continue to scale in both depth and context length, such fragmented optimizations fail to address end-to-end inefficiencies across the full encoder/decoder stack. This paper presents TransFusion, a comprehensive framework for end-to-end Transformer layers, including QKV projections, MHA, LayerNorm, and FFN, as structured Einsum Cascades, enabling precise modelling of data dependencies and execution order. TransFusion introduces DPipe, a unified graph-based scheduler that partitions the Einsum-centric directed acyclic graph (DAG) and applies latency-aware pipelining across hardware hierarchies using dynamic programming (DP). To enable scalable execution under strict memory budgets, TransFusion integrates TileSeek, a Monte Carlo Tree Search (MCTS)-based tiling search algorithm that balances buffer reuse and system constraints. Evaluated across both cloud and edge architecture, TransFusion achieves up to an average of 1.6x speedup on cloud and 2.2x on edge over the prior state-of-the-art, FuseMax, by jointly optimizing inter-layer data reuse, intra-layer pipelining, and operator scheduling.
