Microfluidics is a rapidly growing field that aims to simplify complex analytical procedures by moving them to small-scale devices. A particularly interesting application of microfluidics are so-called Organs-on-Chips, i.e., microfluidic devices that mimic the structure and function of human organs and, therefore, allow studying the effects of drugs and diseases. Recent recognition of the need for standardization in this domain has led to the generation and uptake of new ISO standards—providing the basis of modular and reusable microfluidic building blocks that allow for various organ-on-chip setups. However, designing these building blocks, especially so-called routing blocks that interconnect pumps, cell cultures, and other modules is a cumbersome, repetitive task that is still conducted manually. In this work, we propose a design and routing method that significantly simplifies the design of such routing blocks by fully automating the process of interconnecting components of a microfluidic chip. The evaluation of physical, fabricated routing blocks that were designed using the proposed method showcases its feasibility in real-world applications and its potential to reduce design effort and time significantly. In order to make the work accessible to the microfluidic community, we provide implementations of the resulting methods in the form of a user-friendly, interactive online tool, provided as part of the Munich Microfluidic Toolkit (MMFT).
Homomorphic Encryption (HE) provides strong privacy guarantees by enabling computation directly on encrypted data, but at the cost of substantial computational overhead. Despite recent advances in algorithms and hardware, a gap remains between theoretical feasibility and practical deployment. To close this gap, we advocate a new encrypted computing paradigm that integrates application-level insights with ciphertext encoding to maximize Single-Instruction-Multiple-Data (SIMD) efficiency. Specifically, it comprises (1) pattern-aware encoding along the dominant reduction axes to reduce rotations, (2) Interleaved Assembling to re-densify ciphertexts after dimension reductions, and (3) encryption-aware Rot-structural pruning to exploit weight sparsity in accelerating encrypted neural network computation. On GPUs, it achieves speedups of up to 191× (Cora), 96× (Citeseer), 27× (Pubmed), on graph neural networks (GNNs) and 7.8–27.6× (MNIST and CIFAR-10) on convolutional neural networks (CNNs) such as LeNet, VGG5, ResNet20, all without accuracy loss. We conclude with an outlook on extending this design to large language models and beyond.
Advancing technology nodes have significantly increased the complexity of transistor sizing in analog circuit design. Although artificial intelligence (AI) techniques show potential, their lack of integrated domain expertise often leads to slow convergence in practical applications. We propose ASTRA (Automatic Sizing of Transistors with Reasoning Agents), a novel optimization framework that implements the Model Context Protocol (MCP) to create structured reasoning pathways between Large Language Models (LLMs), domain knowledge bases, and Bayesian Optimization (BO). ASTRA introduces a two-stage process: first, MCP-guided design initialization that leverages Retrieval-Augmented Generation (RAG) to quickly identify feasible regions using gm/ID methodology; and second, BO-based optimization focused on critical transistors, identified through LLM reasoning with data-driven validation. A key innovation of ASTRA is its ability to seamlessly integrate with and enhance virtually any existing transistor sizing algorithm at minimal additional cost. Unlike purely data-driven or black-box LLM approaches, ASTRA maintains traceable decision processes that can be verified and refined. Evaluated on three real-world analog circuits, ASTRA enhances multiple classical optimization methods, achieving up to 4.35× fewer simulation iterations and 2.36× performance improvements, demonstrating its effectiveness as a general open-source framework for advancing analog circuit sizing. 1
Spiking neural networks (SNNs) have emerged as a promising paradigm for energy-efficient neural computation, offering advantages over artificial neural networks (ANNs) by using sparse spike activations. Among SNN models, spiking transformers have shown great potential in achieving high accuracy while maintaining low energy consumption, making them ideal for resource-constrained applications. However, a significant challenge in accelerating Spiking Transformers lies in managing the inherent unstructured sparsity in spike activations. This sparsity introduces substantial hardware overhead, limiting the efficiency of existing accelerators.To address these challenges, we propose SPARTA, an algorithm-hardware co-optimization framework designed specifically for spiking transformers. SPARTA utilizes a spike-aware dynamic token skipping algorithm, which applies reinforcement learning to selectively skip less informative tokens, achieving structured token-level sparsity in both spatial and temporal domains. Additionally, we introduce the spike-aware token prediction algorithm to predict and eliminate inactive tokens, further improving efficiency. Meanwhile, we present a dedicated heterogeneous ReRAM-based Compute-in-Memory (CIM) hardware architecture tailored to support token-level sparsity, which integrates a ReRAM analog CIM engine for linear layer and a token-spike fusion engine for optimized token routing and spike attention. Experimental results show that SPARTA achieves up to 543.1× and 10.2× speedup with 308.0× and 5.2× energy efficiency improvement compared to GPU and the state-of-the-art SNN accelerator "COMPASS", while preserving high model accuracy.
Dynamic programming (DP) plays a crucial role as the backbone of many core optimization algorithms across the physical design flow, including placement, clock tree synthesis, and routing. However, DP methods with quadratic or higher time complexities often face scalability challenges in large-scale designs. In this work, we propose a novel GPU-accelerated DP technique that can be broadly adaptable to various DP-based algorithms. As a case study, we present a GPU-accelerated detailed placement framework targeting mixed-cell-height designs, built upon an optimal DP formulation. By leveraging the massive parallelism of modern GPUs and incorporating advanced cost accumulation strategies, our approach consistently delivers optimal placement solutions while achieving an average runtime reduction of 96.6% and peak speedups exceeding 1600×. This work demonstrates the potential of GPU acceleration not only to overcome runtime bottlenecks but also to enhance design quality in advanced physical design tasks.
