In this study, we designed and fabricated a crystal InOx‐based transistor on a 3.5th generation glass (600 mm × 720 mm) substrate line. The transistor exhibits high field‐effect mobility around 100 m 2 /Vs, an on‐state current higher than that of a low‐ temperature polysilicon‐based transistor, normally‐off characteristics, and high reliability. By combining our organic light‐emitting diode (OLED) patterning technology, we obtained an 8K4K OLED display with high luminance and low power consumption.
Here, we report on the sputtered p‐type Tellurium (Te) thin‐film transistors (TFTs) and circuits with high device performances. We also fabricate and optimize the device characteristics of p‐type Te TFTs with sub‐100 nm channel length using a novel photolithography method. Finally, vertically integrating p‐type TFTs with n‐type ones are demonstrated for monolithic 3‐ dimensional (M3D) applications.
This presentation discusses high‐performance p‐type oxide semiconductors for thin‐film transistors (TFTs). It highlights selenium‐alloyed tellurium in a tellurium sub‐oxide matrix, demonstrating stable p‐channel TFTs with high mobility (10~15 cm 2 /V·s), on/off ratios (10 6 –10 7 ), and long‐term stability, driven by delocalized valence bands and selenium alloying for enhanced transport.
This work demonstrates an effective strategy for improving the electrical performance and positive bias temperature stability (PBTS) of indium gallium zinc oxide (IGZO) thin‐film transistors (TFTs) through synergistic optimization of the IGZO active layer thickness and the integration of an aluminum oxide (Al₂O₃) passivation interlayer. By systematically adjusting the IGZO thickness, a balance between PBTS and threshold voltage (VTH) was achieved. Furthermore, the introduction of an Al₂O₃ interlayer between the IGZO and passivation interfaces significantly enhanced device PBTS under prolonged bias stress. Comprehensive electrical characterizations confirmed that the optimized TFTs exhibited superior performance, including a field‐effect mobility (μ) of 16.7 cm²/V·s, a VTH of 0.4 V and a subthreshold swing (SS) of 72 mV/dec. More importantly, the optimized device exhibits high stability with a VTH drift of only 16.1 mV after 10,000 seconds of bias at 125°C. These results highlight the critical impact of thickness optimization and interface engineering on achieving reliable IGZO TFTs for next‐generation flexible electronics and high‐resolution displays.
In this study, we fabricate polycrystalline ZnO thin films at the interface of PI‐CsPbI 2 Br, resulting in a novel device architecture of ITO/ZnO/PI‐CsPbI 2 Br/CsPbI 2 Br/Ag. Analysis of the device characteristics reveals that this new structure exhibits a significantly reduced dark current (by one order of magnitude). The device demonstrates excellent low‐dose detection capabilities, achieving a detection limit of 118 nGyair s −1 , thus presenting opportunities for further advancements in X‐ray detector technology.
In this work, a simple direct optical patterning technique for WO x nanoparticles was developed. And high‐resolution WO x patterns on the micron scale with attractive electrochromic performance were achieved successfully, for example, optical modulation > 55%, coloration efficiency > 110 cm 2 /C. The results significantly advance the development of high‐resolution and high‐performance non‐emissive electrochromic displays and offer promising prospects for future applications in the academic and research communities.
We report dual‐gate polycrystalline (Poly) In 0.7 Ga 0.3 O thin film transistor (TFT) by spray pyrolysis (SP) process. The dual gate TFTs exhibits saturation mobility (µSAT) of ~40.23 cm 2 V ‐1 s 1 with excellent stability under bias and temperature stress (Δ VTH = 0 V for PBTS, ΔVTH = ‐0.1 V for NBTS). Furthermore, a 2.5‐inch OLED display made of SP poly‐In 0.7 Ga 0.3 O has been demonstrated
This study examines the extent to which displays with ultra‐wide color gamut can accurately reproduce the colors of real‐world scenes. We further identify the specific colors that may present challenges for such displays. The results suggest the ultra‐wide color gamut of QD‐OLEDs enables accurate reproduction of a large and significant portion of the colors we encounter in real life, without needing the full gamut of BT.2020.
We proposed a CMOS‐type scan driver circuit using LTPO TFTs. The core logic part is designed as CMOS logic gates using LTPO TFTs, while the output part is composed of LTPS TFTs only to optimize the design area. In addition, double‐gate structural Oxide TFTs are used to prevent operation in depletion mode. We confirmed that the output signal is stable through the fabricated circuit.
This paper introduces a simple metric for Color Chromaticity Gamut Efficiency (G.E) in terms of color chromaticity in nature. Color Chromaticity Gamut Efficiency is defined as how efficiently a display covers the chromaticity of real objects in nature such as the Standard Object Color Spectra (SOCS) and Pointer's. G.E can be calculated by reproducible area, non‐reproducible area and non‐efficient area regarding real object colors. G.E is higher when the display's color gamut covers ROC efficiently and accurately. Our study found that Adobe + Display P3 has the best color gamut in terms of G.E among various standards including BT.2020. G.E can serve as a guideline for manufacturers when designing display parameters. For instance, a manufacturer might choose to reduce power consumption instead of expanding the color gamut considering G.E. It is expected that consumers could choose a better display with an efficient color gamut, G.E.
In this paper, we introduced indium‐gallium‐zinc oxide (IGZO) synaptic transistors based on charge trapping. By employing a degenerate IGZO trap layer, electron de‐trapping efficiency was significantly improved. Additional process optimization was conducted to address the insufficient device characteristics as a synapse, resulting in notable improvements in program/erase and retention performance. The optimized device exhibits improved electrical characteristics, highlighting their potential as promising candidates for neuromorphic applications.
2D color gamut volume representation of high dynamic range displays is proposed, which is highly correlated with perceptual color attributes. Most of the color volume metrics can approximately measure the reproducible volume range of colors but the measured single volume score and the 3D graphical representation are still not straightforward to understand or compare color characteristics of displays. Therefore, by employing a new 2D representation of 3D color gamut volume, the volume information of a display is intuitively visualized and hence it provides easy way to visually compare color performance of displays. Based on this representation, understanding perceptual color dimensions such as ‘Vividness' and ‘Depth' becomes straightforward.
We propose a scan driver circuit based on p‐type low‐temperature polycrystalline silicon thin‐film transistors (TFTs) capable of stable dual polarity outputs. A novel method of bootstrapping the gate node of pull‐down TFTs directly without a pre‐charging period is used for ripple‐free outputs.
A few Femto‐amperes off leakage current was confirmed with Low Temperature Poly‐Silicon TFTs in OLED Panels by TFT aging method. Since its use in flat panel displays, LTPS TFTs have not been considered to have low off leakage below pico‐amperes because of the grain boundaries defects known as the origin. However, in this paper, it was confirmed that ELA LTPS TFTs can have the value of a few fA, which is the lower leakage current than Single Crystalline Si device [1].
Dynamic power consumption persists in the conventional gate driver circuit even during low‐refresh‐rate operation of OLED displays because oscillation of clock signals is required while outputting switch‐off voltage level. To solve this problem, we propose a novel LTPO‐based gate driver circuit that requires no clock signal oscillation under the low‐refresh‐rate condition, thereby effectively eliminating the dynamic power consumption.
The effect of thickness of gate insulator (GI) film on the performance of hysteresis has been investigated by numerical simulation. With the thickness of GI increasing, the hysteresis become worse. The proportion of surface charge potential on surface potential determined the sensitivity of threshold voltage shift. The thick GI brings the high proportion of surface charge potential, triggering the large threshold voltage shift and then leading to the deterioration of hysteresis. We believe that the hysteresis is greatly influenced by surface charge potential. Rationally designed simulation mode will help us interpret the phenomenon of experiment results comprehensively.
As OLED screens gain increasing recognition in the market, they have become the standard for mainstream high-end products. However, the OLED process is complex, involving numerous steps, and is prone to ESD issues, which negatively impact product yield and pose challenges to OLED production. To improve the anti-ESD ability of the screen process, the mechanism of ESD occurrence is analyzed, and product design is optimized to enhance the anti-ESD ability. Three main approaches are implemented: first, adjusting the ESD circuit design to optimize the electrostatic discharge channel; second, optimizing the structure design of TFT devices to improve their anti-ESD capability; and third, applying an organic film layer to the screen to block electrostatic intrusion. These optimizations successfully reduce the ESD incidence rate from 7.5% to 0.1%.
Micro LED is undergoing extensive research as a leading next-generation display technology. Micro LED utilizes a Pulse Width Modulation (PWM) technique, where the pulse width is directly proportional to the sampled value of the signal. In this study, we successfully improved a pixel circuit that effectively compensates for both positive VTH and negative VTH. When the VTH of the drive TFT controlling the PWM was shifted, the error rate ranged from approximately 0.3% to 0.6% for positive VTH and 0.28% to 0.57% for negative VTH. For the drive TFT controlling the CCG, the VTH shift resulted in error rates of approximately 0.04% to 0.17% for positive VTH and 0.04% to 0.11% for negative VTH.
