A series of SrTiO3 (STO) based temperature compensation dielectrics that were cofireable with the commercial DuPont 951 low-temperature cofireable ceramic (LTCC) were developed. The STO30 dielectric with 30 wt% STO showed the highest positive temperature coefficient of resonant frequency (τf) that was opposite to the τf = -69 ppm/°C of the Dupont 951 LTCC, and was selected to design a temperature-compensated four-pole bandpass filter. The filter shows a near zero τf = 0.7 ppm/°C over a temperature range -20 °C to 80 °C. The variance of insertion loss of the filter over the same temperature span is 0.28 dB. The maximum-difference group delay of the filter is 37 pS. The insertion loss included two SMA connectors at 20 °C is greater than 2.45 dB. A general variational method with the transmission-line technique provided an analytical method to calculate the effective dielectric constant and the characteristic impedance of an arbitrary multilayer strip line structure. With this method, the thickness of STO30 compensation dielectric can be optimized to obtain a nearly full temperature compensation for the filter. The electromagnetic simulation results of the filter agreed well with measured data.
A low-temperature sintering technique enabled by a nanoscale silver paste has been developed for attaching large-area (>100 mm 2 ) semiconductor chips. This development addresses the need of power device or module manufacturers who face the challenge of replacing lead-based or lead-free solders for high-temperature applications. The solder-reflow technique for attaching large chips in power electronics poses serious concern on reliability at higher junction temperatures above 125°C. Unlike the soldering process that relies on melting and solidification of solder alloys, the low-temperature sintering technique forms the joints by solid-state atomic diffusion at processing temperatures below 275°C with the sintered joints having the melting temperature of silver at 961°C. Recently, we showed that a nanoscale silver paste could be used to bond small chips at temperatures similar to soldering temperatures without any externally applied pressure. In this paper, we extend the use of the nanomaterial to attach large chips by introducing a low pressure up to 5 MPa during the densification stage. Attachment of large chips to substrates with silver, gold, and copper metallization is demonstrated. Analyses of the sintered joints by scanning acoustic imaging and electron microscopy showed that the attachment layer had a uniform microstructure with micrometer-sized porosity with the potential for high reliability under high-temperature applications.
This paper describes the electrical contact resistance (ECR) measurements made on thin gold plated (gold plating of ≤ 0.5 μm with a Ni underlayer of ~2 μm) oxygen free high conductivity (OFHC) Cu contacts in vacuum environment. ECR in gold plated OFHC Cu contacts is found to be slightly higher than that in bare OFHC Cu contacts. Even though gold is a softer material than copper, the relatively high ECR values observed in gold plated contacts are mainly due to the higher hardness and electrical resistivity of the underlying Ni layer. It is well known that ECR is directly related to plating factor, which increases with increasing coating thickness when the electrical resistivity of coating material is more than that of substrate. Surprisingly, in the present case it is found that the ECR decreases with increasing gold layer thickness on OFHC Cu substrate (gold has higher electrical resistivity than OFHC Cu). It is analytically demonstrated from the topography and microhardness measurements results that this peculiar behavior is associated with thin gold platings, where the changes in surface roughness and microhardness with increasing layer thickness overshadow the effect of plating factor on ECR.
A silicon interposer with an integrated with SrTiO3 (STO) thin film capacitor that decreases switching noise in high-speed digital circuits has been developed, along with a process to fabricate it. The process for fabricating the capacitor was optimized to reduce the defect density. The identified optimal process conditions are sputter-depositing the STO at 400 °C and using Ru as a bottom electrode. An large-scale integration chip is stacked on the Si interposers using chip-to-wafer bonding, and through-silicon vias (TSVs) are then formed in the interposer. This stacking enables a 50 μm-thick Si interposer to be inserted between a chip and a printed wiring board (PWB). A maximum capacitance density of 2.5 F/cm2 was achieved for a 60-nm-thick STO capacitor in a 20 × 20 mm2 area with 9000 TSVs (50- diameter; 50- depth). The capacitance of slightly more than 1 F in interposer-chip stack samples with 1600 TSVs remained constant during a thermal testing on PWBs for up to 1000 cycles.
In recent times, there has been an ever-growing need for polymer-based multifunctional materials for electronic packaging applications. In this direction, epoxy-Al2O3 nanocomposites at low filler loadings can provide an excellent material option, especially from the point of view of their dielectric properties. This paper reports the dielectric characteristics for such a system, results of which are observed to be interesting, unique, and advantageous as compared to traditionally used microcomposite systems. Nanocomposites are found to display lower values of permittivity/tan delta over a wide frequency range as compared to that of unfilled epoxy. This surprising observation has been attributed to the interaction between the epoxy chains and the nanoparticles, and in this paper this phenomenon is analyzed using a dual layer interface model reported for polymer nanocomposites. As for the other dielectric properties associated with the nanocomposites, the nano-filler loading seems to have a significant effect. The dc resistivity and ac dielectric strength of the nanocomposites were observed to be lower than that of the unfilled epoxy system at the investigated filler loadings, whereas the electrical discharge resistant properties showed a significant enhancement. Further analysis of the results obtained in this paper shows that the morphology of the interface region and its characteristics decide the observed interesting dielectric behaviors.
A primary factor of anisotropic conductive film (ACF) package failure is delamination between the chip and the adhesive at the edge of the chip. This delamination is mainly affected by the thermal shear strain at the edge of the chip. This shear strain was measured on various electronic ACF package specimens by micro-Moire interferometry with a phase shifting method. In order to find the effect of moisture, the reliability performance of an adhesive flip-chip in the moisture environment was investigated. The failure modes were found to be interfacial delamination and bump/pad opening which may eventually lead to total loss of electrical contact. Different geometric size specimens in terms of interconnections were discussed in the context of the significance of mismatch in coefficient of moisture expansion (CME) between the adhesive and other components in the package, which induces hygroscopic swelling stress. The effect of moisture diffusion in the package and the CME mismatch were also evaluated by using the Moire interferometry. From Moire measurement results, we could also obtain the stress intensity factor K . Through an analysis of deformations induced by thermal and moisture environments, a damage model for an adhesive flip-chip package is proposed.
A silicon interposer with an integrated with SrTiO3 (STO) thin film capacitor that decreases switching noise in high-speed digital circuits has been developed, along with a process to fabricate it. The process for fabricating the capacitor was optimized to reduce the defect density. The identified optimal process conditions are sputter-depositing the STO at 400 °C and using Ru as a bottom electrode. An large-scale integration chip is stacked on the Si interposers using chip-to-wafer bonding, and through-silicon vias (TSVs) are then formed in the interposer. This stacking enables a 50 μm-thick Si interposer to be inserted between a chip and a printed wiring board (PWB). A maximum capacitance density of 2.5 F/cm2 was achieved for a 60-nm-thick STO capacitor in a 20 × 20 mm2 area with 9000 TSVs (50- diameter; 50- depth). The capacitance of slightly more than 1 F in interposer-chip stack samples with 1600 TSVs remained constant during a thermal testing on PWBs for up to 1000 cycles.
This paper investigates 2-D finite element analysis to determine the stress and strain distributions across the thickness of ink in single-lap joints. The results of simulations for 10 μm, 20 μm, 30 μm, and 40 μm thickness of ink are presented. Tensile peel and shear stress at the bond free edges change significantly across the thickness of ink, and the maximum shear and peel stresses occur near the overlap joint corner ends. Fourier transform infrared data indicated there was no water absorption in SN9000 ink after a pressure cooker test in which the parameters were 121°C, 100% relative humidity and 2 atm for 96 h. However, the thickness of tin varied when there were differences in the curing temperature. Looking at the experiment and predictions, the confidence level of the results is 91.4%. The findings of this paper help us to understand the relationship between the reliability and the operating temperature of SN9000 for curing temperature design.
Flip-chip bonding on organic sequential buildup substrate technology has been an essential part of semiconductor packaging. In the quest for an ever higher semiconductor performance, there has been a rapidly increasing need for a finer pitch area array of flip-chip joints. However, the pitch has been limited by packaging technology. An advanced buildup substrate for fine pitch flip-chip bonding has been developed to satisfy the requirements for the most advanced semiconductor devices. The advanced substrate features a low-coefficient of thermal expansion (CTE) of 3 ppm°C, a fine pattern of 8 μm in line width and spacing, micro-vias of 25 μm in diameter, and plated through-holes of 100 μm in pitch. These features accommodate the density of a chip I/O of 104 cm-2, which is about ten times greater than that achieved in current organic packaging, and enable significant size reduction of semiconductor chips and the associated packages. The low-CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. This paper describes recent progress in the development of the advanced substrate technology as well as the technical difficulties.
Constructal analysis of tree-shaped microchannels for flow boiling in a disc-shaped body has been carried out to achieve an energy efficient design for chip cooling. n 0 channels touch the center and np channels touch the periphery. Three different complexities have been investigated: the radial flow pattern where n 0 = np ; the one pairing level flow pattern where 2 n 0 = np ; and the two pairing level flow pattern where 4 n 0 = np . The fluid is R-134 a evaporating at a temperature of 300 K. The fluid enters under a saturated state at the inlet and exits at the periphery. Throughout this paper, the constraints are the total volume of ducts V and the radius of the disc R . The degrees of freedom are the number of channels touching the center n 0 , the number of peripheral channels np , and the mass flow rate. The disc, made of copper, is subjected to a heat flux on both its faces. Heat conduction has been simulated in the disc in the radial and angular directions combined with the boiling heat transfer coefficients and the pressure drops along the channels. The temperature field has been calculated and it can be observed that the highest temperature is located where the distance between two microchannels is the largest (most often at the periphery). For characterizing successive diameter ratios for complex structures, Murray's law is shown to be the best solution when using the homogeneous model for calculating the pressure drops. As a first conclusion, we can say that increasing the number of channels decreases the thermal resistance, whatever the complexity is. It is shown that the use of a radial structure with 2 n 0 central channels is more efficient than a one pairing level design with n 0 central channels. Deeper analysis leads to different conclusions. For low pumping power, the radial flow pattern presents the lowest thermal resistance. For medium pumping power, one pairing level design shows the lowest pumping power. For higher pumping power, the design with two pairing levels exhibits the best solution. Finally, complexity is not necessarily the best solution.
Effects of variations of yttrium aluminum garnet:Ce phosphor thickness and concentration on optical consistency of produced white light-emitting diodes (LEDs) including the consistency of brightness and light colors were studied by optical simulation. Five packaging methods with different phosphor locations were compared. Optical models of LED chip and the phosphor were presented and a Monte Carlo ray-tracing simulation procedure was developed. Both color binning and brightness level were used to sort the simulated LEDs to evaluate their optical consistency. Results revealed that the optical consistency of white LEDs strongly depends on how the phosphor thickness and the concentration vary. To obtain desired color binning, conformal phosphor coating is not a favorable packaging method due to its low brightness level and poor brightness consistency by large shifts of the brightness level as the phosphor thickness and concentration varying. Planar remoter phosphor improves the brightness level and its consistency, but realization of high color consistency becomes more difficult due to its smaller variation ranges of the phosphor thickness and concentration. Hemispherical remoter phosphor can fulfill the requirements of both high color consistency and high brightness consistency due to its capability of larger variation ranges of the phosphor thickness and concentration. By applying this method with thick phosphor thickness or high phosphor concentration, this method can be a promising packaging method for the low cost production.
The use of anisotropic conductive adhesives (ACA) in flip chip interconnection technology has become very popular because of their numerous advantages. The ACA process can be used in high-density applications and with various substrates as the bonding temperature is lower than that in the soldering process. In this paper, six test lots were assembled using two anisotropic conductive adhesive films (ACF) and four different FR-4 substrates. FR-4 was chosen as it is an interesting alternative for making low-cost high-density interconnections. Some of the chips were thinned to study the effect on reliability. To study the effect of bonding pressure, four different pressures were used in every test lot. The reliability of the assembled test samples was studied in a temperature cycling test carried out between temperatures of -40°C and 125°C for 10 000 cycles. A finite element model (FEM) was used to study the shear stresses in the interconnections during the test. Marked differences between the substrates were seen. The substrate thinning and also the chip thinning increased the reliability of the test samples. From the FEM, it was seen that both decreased the shear stress in the adhesive, which is assumed to be the reason for the increased reliability. A significant difference was seen in the reliability between the ACFs. This was probably caused by differences in the conductive particle materials and the T g values and of the ACFs. In addition, the bump material used with the ACFs varied, which most likely affected the reliability of the test samples.
Silicone materials with a relatively high-refractive index have been introduced for the encapsulation of high-power light-emitting diodes (LEDs), and LEDs with relatively short wavelengths. However, most of those existing silicone encapsulants still suffer from thermal and radiation induced degradations and thus lead to reliability issues and a shorten lifetime. A new high-performance silicone has been developed and its performance is compared with other commercial silicone and optical grade epoxy in high-power white LEDs. The new materials had been found to suffer less loss in the lumen output during the aging test and high-temperature/high-humidity test, as well as the Joint Electron Devices Engineering Council (JEDEC) reliability test. It is concluded that this material is excellent for the packaging of high-power white LEDs and high-power colored LEDs, because of its ability in maintaining high-transparency and great radiation/thermal resistance.
Recently, silicon carbide power devices have been receiving attention for applications above 300 °C. For high-temperature applications, the die attached for these devices has to withstand the maximum operating temperature. In this paper, a transient liquid phase (TLP) die attach technique was demonstrated for two binary alloy systems, Ag-In and Au-In, on Si3N4 substrates. A nearly void-free joint was developed using the Ag-In alloy. Two inter-metallic phases of Agln2 and Ag2ln, along with pure Ag were identified. After annealing at 400 °C, the silver appears to be more evenly spread to form a silver-rich Ag-In alloy with a Ag composition of 70-75 wt.%, even though a nearly pure silver phase is still found in the region where the silver was initially deposited on the Si3N4 substrate. For the Au-In system, there was no indication of bonding degradation at the interface after annealing at 400 °C for 100 h in air. Two inter-metallic phases, Auln and Auln2, along with pure gold, were identified in the Au-In TLP joint. After annealing, the bonding interface became a more Au-rich Au-In alloy. The die attach pull strength, after thermal annealing, increased to approximately twice the minimum strength. The uniformity of the bonds improves and they become more homogeneous because the formation of intermetallic phases continues during thermal annealing.
Proposed uses of solid-state thermoelectric micro-coolers for hot spot remediation have included the formation of a superlattice layer on the back of the microprocessor chip, but there have been few studies on the cooling performance of such devices. This paper provides the results of 3-D, electrothermal, finite element modeling of a superlattice microcooler, focusing on the hot spot temperature and superlattice surface temperature reductions, respectively. Simulated temperature distributions and heat flow patterns in the silicon, associated with variations in microcooler geometry, chip thickness, hot spot size, hot spot heat flux, and superlattice thickness are provided. Comparison is made to hot spot cooling achieved by the Peltier effect in the silicon microprocessor chip itself. The numerical results suggest that, for a variety of operating conditions and geometries, while increasing the superlattice thickness serves to decrease the exposed superlattice surface temperature, it is ineffective in reducing the hot spot temperature below that due to the silicon Peltier effect.
A synthetic jet is a zero-net-mass-flux device, which synthesizes stagnant air to form a jet, and is potentially useful for cooling. Due to the inherent suction and ejection processes in a synthetic jet, its utility in a confined enclosure is not obvious. The synthetic jet impingement heat transfer characteristics inside a rectangular duct are studied in this paper. In addition, the effect of cross-flow created using either fans or another synthetic jet on its heat dissipation capability is examined. Experiments are conducted for different jet Reynolds numbers (Re), in the range of 950-4000, at different offset positions of the synthetic jet with respect to a heated block flush mounted on one surface of the duct. The height of the duct is the same (25 mm) for all measurements while the width is varied between 110 mm and 330 mm in order to examine the effect of confinement on the heat transfer coefficient. The change in the width of the duct is found to have a negligible effect on heat transfer. The heat transfer coefficient is found to be more with synthetic jet direct impingement (150 W/m2 · K) than with combined flow (both impingement and cross-flow) (134 W/m2 · K) or with only cross-flow (45 W/m2 · K) in the duct. The offset of the synthetic jet from the center of the heated block is found to drastically reduce the heat transfer. These results are expected to be useful for designing synthetic jet-based cooling solutions.
Due to the thin structure used in planar packaging, the electric field intensity within the encapsulation is high, leading to degradation of the dielectric performance. To resolve this issue, a metal posts interconnected parallel plate structure (MPIPPS) is used to reduce the high electric field concentration in the power module. However, the high bonding joint in MPIPPS causes large thermo-mechanical stress within the solder layers. This paper proposes a methodology to optimize the joint height based on a trade-off between the thermo-mechanical performance and dielectric performance of the power module. The impact of the joint height on thermo-mechanical stress and dielectric performance of the module is investigated quantitatively using ANSYS and Maxwell simulations. The results show that using a 0.4mm joint height and Nusil R-2188 encapsulation, the power module can achieve 3 kV breakdown voltage. Experimental results agree with the simulation results.
In this paper, durability tests were conducted on both SAC305 and Sn37Pb solder interconnects using both harmonic and random vibration. The test specimens consist of daisy-chained printed wiring boards (PWBs) with several different surface-mount component styles. Modal testing was first conducted on a test PWB to determine the natural frequencies and mode shapes. The PWB was then subjected to narrow-band excitation at its first natural frequency. Electrical continuity of the daisy-chain nets was monitored to measure the time-to-failure (and hence cycles-to-failure) of the interconnects. The response history of the PWB was recorded with strain gages located near the components of interest. Finite element analysis (FEA) was conducted for each component type, to estimate the transfer function between the flexural strain of the PWB and the strain in the critical solder joint. The predicted strain transfer function was then combined with the measured PWB strain response history to estimate the strain history in the critical solder joints. The solder strain history was used, in conjunction with the failure history, to estimate lower bounds for the fatigue durability (S-N curves) of the solder interconnects. In the first part of this paper, the results show that the SAC305 interconnects are marginally less durable than Sn37Pb interconnects for the harmonic excitation range used in this paper. The durability model constants are found to be very sensitive to the solder stress-strain curve assumed in the FEA. Since the stress-strain properties reported in the literature for these solder alloys vary significantly, the solder stress-strain curves were parametrically varied in the FEA, to assess the resulting effect on the estimated S-N curves. In the second part of this paper, random-vibration tests were conducted to assess durability under step-stress, broad-band excitation. Conventional cycle counting techniques were used to quantify the random excitation histories in terms of range distribution functions. Using the same time-domain vibration fatigue analysis used earlier for narrow-band excitation, the durability trend for the corresponding SAC305 and Sn37Pb solder interconnects under broad-band excitation was found to be similar to that found earlier under harmonic vibration excitation. Comparison between the durability prediction and test results provides a good understanding of the effect of stress-strain behavior on the fatigue constants of these solder materials. The best set of material properties was then used to verify the durability of leadless chip resistor interconnects under quasi-static mechanical cycling.
This paper discusses the design and use of low-temperature (850°C to 950°C) cofired ceramic (LTCC) planar magnetic flyback transformers for applications that require conversion of a low-voltage to high-voltage (> 100-V) with significant volumetric constraints. Measured performance and modeling results for multiple designs show that the LTCC flyback transformer design and construction imposes serious limitations on the achievable coupling, and significantly impacts the transformer performance and output voltage. This paper discusses the impact of various design factors that can provide improved performance by increasing transformer coupling and output voltage. The experiments performed on prototype units demonstrate LTCC transformer designs capable of greater than 2-kV output. Finally, the paper investigates the effect of the LTCC microstructure on transformer insulation. Although this paper focuses on generating voltages in the kV range, the experimental characterization and discussion presented in this paper applies to designs requiring lower voltage.
