We discuss dynamic real-time analysis from multimodal data fusion for contextual risk identification to generate "Risk Maps "for the workplace, resulting in timely identification of hazards and associated risk mitigation. It includes new machine/deep learning, analytics, methods, and its applications that deal with the unconventional data collected from pictures, videos, documents, mobile apps, sensors/Internet of Things, Occupational Safety and Health Administration (OSHA) rules, and Building Information Model (BIM) Models. Speccally, we describe a number of advances and challenges in this field with applications of computer vision, natural language processing, and sensor data analysis. Applications include automated cause identification, damage prevention, and disaster recovery using current and historical claims data and other public data. The methods developed can be applied to any given situation with different groups of people, including first responders. Finally, we discuss some of the important nontechnical challenges related to business practicality, privacy, and industry regulations.
Stipulations in the 2014 Collaboration of Oak Ridge, Argonne, and Livermore (CORAL) joint procurement activity not only motivated a fundamental change in IBM's high-performance computer design, which refocused IBM power systems on compute nodes that can scale to 200 petaflops with access to 2.5 PB of memory, but also served the commercial market for single-server applications. The distribution of both processing elements and memory required a careful look at data movement. The resultant AC922 POWER9 system features NVIDIA V100 GPUs with cache line access granularity more than double the 10 bandwidth of PCIe Gen3, and low-latency interfaces interconnected by the state-of-the-art dual-rail Mellanox CAPI EDR HCAs running at 50 Gb/s. With processing units designed to operate at 250 and 300 W, a single system can produce up to 3,080 kW. The overall CORAL solutions achieved power usage effectiveness rankings in the top ten on the Green500. Previous power designs used uniquely designed cabinets and scaled-up infrastructure to achieve efficiency. For successful commercial use, our design uses industry-standard 19-in drawers and racks. Both air- and water-cooled solutions allow for use in a wide range of customer environments. This article documents the novel design features that facilitate data movement and enable new coherent programming models. It describes how three generations of system designs became the foundation for the CORAL contract fulfillment and illustrates key features and specifications of the final product.
Ability to efficiently offload computational workloads to graphic processing units (GPUs) is critical for the success of hybrid CPU-GPU architectures, such as the Summit and Sierra supercomputing systems. OpenMP 4.5 is a high-level programming model that enables the development of architecture- and accelerator-independent applications. This article describes aspects of the OpenMP implementation in the IBM XL C/C++ and XL Fortran OpenMP compilers that aid programmers to achieve performance objectives. This includes an interprocedural static analysis the XL optimizer uses to specialize code generation of the OpenMP distribute parallel do loop within the dynamic context of a target region, and other compiler optimizations designed to reduce the overhead of data transferred to an offloaded target region. We introduce the heuristic used at runtime to select optimal grid sizes for offloaded target team constructs. These tuned heuristics lead to an average improvement of 2x in the runtime of several target regions in the SPEC ACCEL V1.2 benchmark suite. In addition to performance enhancement, this article also presents an advanced diagnostic feature implemented in the XL Fortran compiler to aid in debugging OpenMP applications ojjloaded to accelerators.
The IBM z15 is designed to meet the requirements of a range of data centers, while reducing costs through increased density, configuration flexibility, and cooling efficiency. The z15 is a continuation and broadening of the physical transformation of the mainframe that began with the IBM z14 ZR1/LR1, which introduced the new "true 19-in" frame. A maximum configuration z15 delivers greater than 30% additional compute capacity per watt than z14, and maintains approximately the same maximum system footprint, while enabling significant floor space reduction for most configurations. The z15 introduces the choice of integrated 2N power using either intelligent power distribution units or bulk power, also supporting most data centers including hot/cold-aisle containment, raised-floor and nonraised-floor, and top and bottom-exit I/O and power. The z15 supports the ASHRAE A3 (fourth edition) environment, providing efficiency advantages by reducing humidification requirements. The z15 maintains the value of a system that is preconfigured/pretested before shipping. Innovations in packaging, I/O cabling, controls, and testing are put in the context of the latest data center trends. The capabilities of new tools to estimate power, weight, airflow, heat extracted to water for water-cooled systems as well as 3-D and computational fluid dynamics models to aid in the planning for the system are described.
The IBM z15 processor power management enhances several on-chip power management techniques over z14 processor with a specific focus on reducing response time for voltage droop management. The IBM z15 processor puts a specific emphasis on proactive voltage droop management strategy to reduce conservative static guard band that is added to the supply voltage in order to protect against worst-case voltage droops. The z15 processor relies on selected events from the earlier stages of a deep pipeline processor as indicators to predict sharp changes in the power consumption over a short period of time. The early information of the selected events allows to throttle the execution flow through the processor pipeline and prevents the sharp power change before it takes place and thus reduces the voltage droop. In z15, as one of the proactive schemes, we combine both the digital power-proxies, which are direct indicators of the processor activity and the Critical Path Monitors (CPMs) to give an earlier and proactive indication of voltage droop events. This proactive indication provides enough time for the throttle actuation circuits to prevent the voltage droop. CPMs act as real-time timing margin indicators, and power-proxies act to serve as the activity monitors.
This article discusses how the product development cycle is being transformed with “Artificial Intelligence” (AI) for the first time in zSeries history. This new era of AI, under the project name IBM Z Development Transformation (zDT), has allowed the team to grow and learn new skills in data science. This transformation forces change structurally in how data is prepared and stored. In z14, there were incremental productivity gains with enhancements to automation with eServer Automation Test Solution and a technology data analysis engine called zDataAssist. However, in z15, AI will significantly accelerate our efficiency. This article explains how Design Thinking and Agile principles were used to identify areas that are of high impact and feasible to implement: 1) what and how data is collected via System Test Event Logging and Analysis engine, Problem ticket management system (Jupitr), and Processor data analysis engine (Xrings); 2) problem identification, analysis, and management (AutoJup) along with Intelligent Recovery Verification Assistant; 3) product design documentation search engine (AskTheMachine); and 4) prototype microprocessor allocation processes Intelligent Commodity Fulfillment System using Machine Learning. This article details the approach of these areas for z15, the implementation of these solutions under the zDT project, as well as the results and future work.
The IBM z15 supports the new IBM Z Hardware Management Appliance optional feature, which provides redundant Hardware Management Consoles (HMCs) and Support Elements (SEs) that run on redundant physical servers inside the CPC (Central Processor Complex) frame. This eliminates the need for having to manage one or more separate physical servers for HMCs outside of the frame. This article describes the host HMC/KVM (kernel-based virtual machine) and Virtual SE environment, which is completely managed by IBM Z firmware as a true appliance. It also illustrates the firmware integrity monitoring environment for the host HMC/KVM extended to the Virtual SE to provide secure boot protection for firmware and continuous monitoring and the utilization of a shared trusted platform module. It describes how physical system errors are processed by problem analysis firmware running on the Virtual SE, thereby enabling online guided repair instructions running on the Virtual SE to be used for both HMC and SE detected errors. This article will shares the innovative design basics of the IBM Z Hardware Management Appliance feature, which has significant positive impact potential for both clients and IBM.
The IBM Z central processor (CP) and storage controller (SC) chips contain hardware and firmware to serve selfboot and secure boot needs. Selfboot initializes the CP/SC chips from hardware and firmware, which reside in each chip module. This establishes a core root of trust and also guarantees a boot time that is independent of the system configuration, which is key for large enterprise class systems consisting of multiple drawers and chips. Secure boot is built on this core root of trust and is used to authenticate the firmware loaded from system memory prior to execution of that firmware. Selfboot and secure boot also guarantee the integrity of the CP and SC chips by restricting hardware and memory accesses through debug or service interfaces during boot, runtime, and code update phases. In this article, we describe the basic hardware and firmware concepts that are implemented and enabled for the z 15 CP and SC chips.
The latest-generation IBM Z processor provides enhanced performance and compute capacity compared to its IBM z14 predecessor. This article describes some of the major improvements in both process and design including out-of-order load-and-store sequencing, single-instruction multiple-data and floating point enhancements, a new modulo arithmetic engine for accelerating elliptic curve cryptography, a hardware sort accelerator, and a workflow that modernized the development of these features. Outside of the central processing unit (CPU), the cache sizes have increased on all levels, and each processor chip now contains 12 CPUs. System topology changes have been introduced allowing up to five drawers to exist in a fully populated system. The processor cache subsystem includes numerous improvements in the area of fetch, store, and cache management policies aimed at speeding up both traditional data serving workloads and highly virtualized environments alike.
Controlling access to and privacy of data within the enterprise can prove to be a formidable task with increased complexity and management overhead encountered as the granularity of access control is increased. Fibre Channel is the premier enterprise storage transport, so an organization's most sensitive data flows over Fibre Channel links within and across datacenters. In this article, we discuss a new, easy way to deploy innovation for Fibre Channel connections that ensures data is exchanged only between trusted servers and storage controllers, while also enabling the integrity and confidentiality of the data in flight between the trusted entities. We explain how the components of IBM Fibre Channel Endpoint Security are configured to work together to provide protection from insider threats, requiring minimal steps to deploy, fully controlled via policy, and transparent to applications, middleware, and operating systems.
Every new machine generation of IBM Z brings with it an increase in number of physical processors and memory capacity. Some generations can also bring change in the physical configuration of the server. The z15 for example, can have from one to five drawers instead of a maximum of four on the z14. As another example, z15 has fixed two chips per node versus the two or three chips per node on z14. The logical partitions on the other hand can come in various configurations, including "Dedicated" logical partition, shared "Hiperdispatch YES" logical partition, and shared "Hiperdispatch = NO" partition. Each of the partition types can request as many logical processors and memory as the machine generation will allow, which is usually less than the physical resources available on the machine. The optimal placement of logical partitions on the physical server, given its configuration, is an NP-hard problem. Memory access latency and cache usage play vital roles in the performance of logical partitions, and it is imperative that placement is optimal. Moreover, on z15, the integrated facility for linux processors and internal coupling facility processors can be moved from one chip to another, during reoptimization of partition placement, in addition to general-purpose and IBM Z integrated information processors that are already allowed to be moved, compounding the placement problem. This article describes the changes made to the Processor Resource/Systems Manager (PR/SM) heuristic placement algorithm for z15 and how it surmounts the problems inherent for optimal placement of logical partitions.
Timekeeping and highly accurate, precise time synchronization are key requirements for modern information technology systems. While true for several industries, this is especially true for industries involved in transaction processing such as the financial industry. As such, the IBM Z Sysplex needs highly accurate timing/timekeeping and synchronization technology to ensure data integrity, and to also provide the ability to reconstruct a database based upon logs. Recently enacted changes and new regulatory requirements, both in Europe and the United States, have brought increasing attention to time synchronization accuracy. These regulations spurred an interest, both from IBM Z and from our IBM Z clients, in the IEEE 1588 Precision Time Protocol (PTP) being implemented in IBM Z This article explains the history of PTP, PTP technology, the regulations that led IBM to introduce PTP to IBM Z, PTP's implementation on IBM Z, and IBM's involvement and leadership in the development of the PTP technology and standards going forward.
System Recovery Boost on the IBM z15 server expedites planned operating system shutdown, either planned or unplanned operating system initial program load (IPL), middleware and workload restart and recovery, and the client workload execution that follows, to accelerate service restoration around downtime. It does this by providing limited-duration "boost periods" that deliver significant usable additional processor capacity and parallelism. On subcapacity machine models, it provides a boost in processor speed by running the general-purpose processors at full-capacity speed, for the boosting LPARs only, and only during the boost periods. It makes all available processing capacity defined to the boosting images available to process any kind of work, "blurring" general-purpose processor and specialty processor capacity together during the boost period. System Recovery Boost also expedites and parallelizes processor reconfiguration actions that may be part of the client's overall restart and recovery process, as orchestrated by Geographically Dispersed Parallel Sysplex (GDPS) automation. Optionally, System Recovery Boost provides the ability to add additional processor capacity from the client's unused "dark cores" via activation of a new type of temporary capacity record. All of this can be accomplished without increasing the client's IBM software billing costs or the processor consumption associated with the clients workload during these boost periods.
The IBM z15 processor chip contains a new hardware component to perform DEFLATE compliant compression and decompression. The Integrated Accelerator for zEnterprise Data Compression is based on a high-frequency DEFLATE pipeline and includes a hardware generator for dynamic Huffman tables. Accessible as an architected instruction, this engine has been designed for straightforward exploitation by software and is easily available to any application in the problem state. A brand-new hardware/firmware integration model has been developed to provide this complex functionality without imposing restrictions on data patterns or data sizes and without impacting system responsiveness. This article describes the concept, implementation, and verification of DEFLATE, compliant compression acceleration in z15 across both hardware and firmware. It illustrates various challenges that result from incorporating complex data-dependent and data-intense functionality like DEFLATE as an architected instruction and discusses how solutions in hardware/firmware codesign have been applied to overcome these challenges.
System security is currently a main focus area for all IT infrastructure providers. New system features like pervasive encryption, the transition to cloud-based offerings, and the demand for quantum-safe platforms demand increased cryptographic performance as well as more cryptographic agility. The new IBM 4769 Cryptographic Coprocessor addresses these trends. It brings performance improvements that match the requirements of the new IBM z15. A combination of newly available features allows IBM z15 to scale to greater than 5,000 Virtual Hardware secure modules per system and makes it suitable to support virtualized client environments such as cloud-scale datacenters. To meet the dense packaging and energy requirements of those data centers, the form factor and power consumption of the card were reduced significantly. The card also offers an expanded set of algorithms to support state-of-the-art as well as future workloads. For the first time, the user interface provides access to a selected set of quantum-safe algorithms. Infrastructure extensions add hardware-embedded, attestation-friendly trusted boot services, which improve system resiliency by providing hardware enabled measurements of the secure and trusted boot process. These extensions simultaneously simplify the security certifications built on them. This article provides an overview of the IBM 4769 cryptographic coprocessor, highlighting security characteristics, internal hardware, form factor, and enhanced firmware.
The IBM Z processor continues to improve over previous System Z processors, but for the first time it does so without a technology improvement as the baseline enabler. The IBM z15 was designed in the same 14-nm High-Performance GLOBALFOUNDRIES technology as the IBM z14 and yet still added 20% more cores, doubled the L3 cache, and increased the L2 cache by a third while also adding a third peripheral component interconnect express (PCIe) port to the chip and an elliptic curve cryptography engine into each core. This article discusses the design, tool, and methodology enhancements required to increase the design content so significantly while maintaining the chip size and power limits from the previous z14 design. This article also discusses other design and methodology improvements that were made possible via the deeper understanding of the technology and how to more fully leverage it in a second generation.
IBM z15 replaces the former I/O attached accelerator for DEFLATE, zEnterprise Data Compression (zEDC) Express, with an on-chip accelerator that can be synchronously accessed via an instruction. The integration of this new accelerator in the z/OS software stack has been designed to maintain a consistent user experience for software packages that used the previous technology, while still allowing the enhanced aspects of the new technology to deliver the additional value. Two different access paths for DEFLATE have been created in z/OS to accomplish both goals. For user space programs that utilize the zlib API, z/OS directly executes the instruction synchronously, which avoids overhead and reduces latency. Authorized users continue to utilize existing infrastructure and have the Service Assist Processors (SAP) perform compression in an asynchronous fashion on their behalf. The SAP receives information about the requested task via a thin and efficient communication path to z/OS, invokes the instruction in a well-defined fashion, and returns the result to z/OS.This article describes the integration of DEFLATE acceleration in z15 into the z/OS software stack in both synchronous and asynchronous mode and presents the resulting performance for selected workloads.
The IBM z15 is built to support users to deliver mission-critical workloads and services in a hybrid cloud environment. In this article, we describe the new capabilities that are intended to fit the platform into private and public cloud frameworks. This work is rooted in the broader IBM cloud strategy and point-of-view and based on ongoing efforts to identify and address critical pain-points for a key set of enterprise clients through applying Enterprise Design Thinking practices. By outlining the hardware, firmware, and software support added for z15, we show how we have been able to integrate the IBM Z platform into the IBM Cloud infrastructure. We also discuss how cloud-focused technologies and tooling enable users to access, deploy, and lifecycle manage z/OS resources and services for a seamless cloud experience.
